forked from github/verilator
71 lines
1.6 KiB
Systemverilog
71 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Fib;
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function int get_fib(int n);
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if (n == 0 || n == 1)
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return n;
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else
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return get_fib(n - 1) + get_fib(n - 2);
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endfunction
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endclass
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class FibStatic;
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static function int get_fib(int n);
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if (n == 0 || n == 1)
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return n;
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else
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return get_fib(n - 1) + get_fib(n - 2);
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endfunction
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endclass
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class Factorial;
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static function int factorial(int n);
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return fact(n, 1);
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endfunction
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static function int fact(int n, int acc);
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if (n < 2)
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fact = acc;
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else
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fact = fact(n - 1, acc * n);
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endfunction
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endclass
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class Getter3 #(int T=5);
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static function int get_3();
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if (T == 3)
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return 3;
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else
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return Getter3#(3)::get_3();
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Fib fib = new;
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Getter3 getter3 = new;
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if (fib.get_fib(0) != 0) $stop;
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if (fib.get_fib(1) != 1) $stop;
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if (fib.get_fib(8) != 21) $stop;
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if (FibStatic::get_fib(0) != 0) $stop;
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if (FibStatic::get_fib(1) != 1) $stop;
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if (FibStatic::get_fib(8) != 21) $stop;
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if (Factorial::factorial(0) != 1) $stop;
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if (Factorial::factorial(1) != 1) $stop;
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if (Factorial::factorial(6) != 720) $stop;
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if (getter3.get_3() != 3) $stop;
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if (Getter3#(3)::get_3() != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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