Support recursive methods (#3987)

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Ryszard Rozak 2023-03-02 03:07:37 +01:00 committed by GitHub
parent faf3804b9a
commit 2c60c5f816
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4 changed files with 105 additions and 3 deletions

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@ -900,6 +900,7 @@ private:
bool m_doV = false; // Verilog, not C++ conversion
bool m_doGenerate = false; // Postpone width checking inside generate
bool m_hasJumpDelay = false; // JumpGo or Delay under this while
bool m_underRecFunc = false; // Under a recursive function
AstNodeModule* m_modp = nullptr; // Current module
const AstArraySel* m_selp = nullptr; // Current select
const AstNode* m_scopep = nullptr; // Current scope
@ -1457,6 +1458,7 @@ private:
if (!thensp->lhsp()->sameGateTree(elsesp->lhsp())) return false;
if (!thensp->rhsp()->gateTree()) return false;
if (!elsesp->rhsp()->gateTree()) return false;
if (m_underRecFunc) return false; // This optimization may lead to infinite recursion
return true;
}
bool operandIfIf(const AstNodeIf* nodep) {
@ -3128,6 +3130,11 @@ private:
VL_DO_DANGLING(replaceConstString(nodep, nodep->name()), nodep);
}
}
void visit(AstNodeFTask* nodep) override {
VL_RESTORER(m_underRecFunc);
if (nodep->recursive()) m_underRecFunc = true;
iterateChildren(nodep);
}
void visit(AstFuncRef* nodep) override {
iterateChildren(nodep);

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@ -5221,9 +5221,13 @@ private:
// Grab width from the output variable (if it's a function)
if (nodep->didWidth()) return;
if (nodep->doingWidth()) {
UINFO(5, "Recursive function or task call: " << nodep);
nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function or task call: "
<< nodep->prettyNameQ());
if (nodep->classMethod()) {
UINFO(5, "Recursive method call: " << nodep);
} else {
UINFO(5, "Recursive function or task call: " << nodep);
nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function or task call: "
<< nodep->prettyNameQ());
}
nodep->recursive(true);
nodep->didWidth(true);
return;

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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2020 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

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@ -0,0 +1,70 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
class Fib;
function int get_fib(int n);
if (n == 0 || n == 1)
return n;
else
return get_fib(n - 1) + get_fib(n - 2);
endfunction
endclass
class FibStatic;
static function int get_fib(int n);
if (n == 0 || n == 1)
return n;
else
return get_fib(n - 1) + get_fib(n - 2);
endfunction
endclass
class Factorial;
static function int factorial(int n);
return fact(n, 1);
endfunction
static function int fact(int n, int acc);
if (n < 2)
fact = acc;
else
fact = fact(n - 1, acc * n);
endfunction
endclass
class Getter3 #(int T=5);
static function int get_3();
if (T == 3)
return 3;
else
return Getter3#(3)::get_3();
endfunction
endclass
module t (/*AUTOARG*/);
initial begin
Fib fib = new;
Getter3 getter3 = new;
if (fib.get_fib(0) != 0) $stop;
if (fib.get_fib(1) != 1) $stop;
if (fib.get_fib(8) != 21) $stop;
if (FibStatic::get_fib(0) != 0) $stop;
if (FibStatic::get_fib(1) != 1) $stop;
if (FibStatic::get_fib(8) != 21) $stop;
if (Factorial::factorial(0) != 1) $stop;
if (Factorial::factorial(1) != 1) $stop;
if (Factorial::factorial(6) != 720) $stop;
if (getter3.get_3() != 3) $stop;
if (Getter3#(3)::get_3() != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule