forked from github/verilator
Support recursive methods (#3987)
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@ -900,6 +900,7 @@ private:
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bool m_doV = false; // Verilog, not C++ conversion
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bool m_doGenerate = false; // Postpone width checking inside generate
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bool m_hasJumpDelay = false; // JumpGo or Delay under this while
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bool m_underRecFunc = false; // Under a recursive function
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AstNodeModule* m_modp = nullptr; // Current module
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const AstArraySel* m_selp = nullptr; // Current select
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const AstNode* m_scopep = nullptr; // Current scope
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@ -1457,6 +1458,7 @@ private:
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if (!thensp->lhsp()->sameGateTree(elsesp->lhsp())) return false;
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if (!thensp->rhsp()->gateTree()) return false;
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if (!elsesp->rhsp()->gateTree()) return false;
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if (m_underRecFunc) return false; // This optimization may lead to infinite recursion
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return true;
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}
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bool operandIfIf(const AstNodeIf* nodep) {
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@ -3128,6 +3130,11 @@ private:
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VL_DO_DANGLING(replaceConstString(nodep, nodep->name()), nodep);
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}
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}
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void visit(AstNodeFTask* nodep) override {
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VL_RESTORER(m_underRecFunc);
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if (nodep->recursive()) m_underRecFunc = true;
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iterateChildren(nodep);
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}
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void visit(AstFuncRef* nodep) override {
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iterateChildren(nodep);
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@ -5221,9 +5221,13 @@ private:
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// Grab width from the output variable (if it's a function)
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if (nodep->didWidth()) return;
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if (nodep->doingWidth()) {
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UINFO(5, "Recursive function or task call: " << nodep);
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function or task call: "
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<< nodep->prettyNameQ());
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if (nodep->classMethod()) {
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UINFO(5, "Recursive method call: " << nodep);
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} else {
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UINFO(5, "Recursive function or task call: " << nodep);
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: Recursive function or task call: "
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<< nodep->prettyNameQ());
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}
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nodep->recursive(true);
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nodep->didWidth(true);
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return;
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21
test_regress/t/t_recursive_method.pl
Executable file
21
test_regress/t/t_recursive_method.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2020 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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70
test_regress/t/t_recursive_method.v
Normal file
70
test_regress/t/t_recursive_method.v
Normal file
@ -0,0 +1,70 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Fib;
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function int get_fib(int n);
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if (n == 0 || n == 1)
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return n;
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else
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return get_fib(n - 1) + get_fib(n - 2);
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endfunction
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endclass
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class FibStatic;
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static function int get_fib(int n);
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if (n == 0 || n == 1)
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return n;
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else
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return get_fib(n - 1) + get_fib(n - 2);
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endfunction
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endclass
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class Factorial;
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static function int factorial(int n);
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return fact(n, 1);
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endfunction
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static function int fact(int n, int acc);
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if (n < 2)
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fact = acc;
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else
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fact = fact(n - 1, acc * n);
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endfunction
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endclass
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class Getter3 #(int T=5);
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static function int get_3();
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if (T == 3)
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return 3;
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else
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return Getter3#(3)::get_3();
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Fib fib = new;
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Getter3 getter3 = new;
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if (fib.get_fib(0) != 0) $stop;
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if (fib.get_fib(1) != 1) $stop;
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if (fib.get_fib(8) != 21) $stop;
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if (FibStatic::get_fib(0) != 0) $stop;
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if (FibStatic::get_fib(1) != 1) $stop;
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if (FibStatic::get_fib(8) != 21) $stop;
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if (Factorial::factorial(0) != 1) $stop;
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if (Factorial::factorial(1) != 1) $stop;
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if (Factorial::factorial(6) != 720) $stop;
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if (getter3.get_3() != 3) $stop;
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if (Getter3#(3)::get_3() != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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