forked from github/verilator
62 lines
1.6 KiB
Systemverilog
62 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Anderson Ignacio da Silva.
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// SPDX-License-Identifier: CC0-1.0
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package test_pkg;
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localparam [31:0] test_arr [4][4:0]
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= '{
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'{'h0000, 'h1000, 'h2000, 'h3000, 'h4000},
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'{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF},
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'{ 'd0, 'd0, 'd0, 'd0, 'd0},
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'{ 'd0, 'd1, 'd2, 'd3, 'd4}
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};
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typedef struct packed{
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logic [7:0] val_1;
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logic [7:0] val_2;
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} test_ret_t;
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endpackage
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module t import test_pkg::*; (clk);
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input clk;
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function automatic test_ret_t test_f(logic [31:0] val);
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test_ret_t temp;
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temp = test_ret_t'(0);
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for (int i=0; i<5; i++) begin
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if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin
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temp.val_1 = test_arr[2][i][7:0];
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temp.val_2 = test_arr[3][i][7:0];
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end
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end
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return temp;
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endfunction
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test_ret_t temp;
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logic [31:0] random;
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int cyc;
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bit [63:0] sum;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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random <= {17'b0, cyc[3:0], 11'b0};
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temp <= test_f(random);
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`ifdef TEST_VERBOSE
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$display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2);
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`endif
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if (cyc > 10 && cyc < 90) begin
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sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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end
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else if (cyc == 99) begin
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$displayh(sum);
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if (sum != 64'h74d34ea7a775f994) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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