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Internals: Untabify some embedded tabs.

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This commit is contained in:
Wilson Snyder 2021-11-13 10:46:25 -05:00
parent 27883b52d6
commit 3a5cbd5b67
198 changed files with 638 additions and 638 deletions
test_regress/t
t_EXAMPLE.vt_alw_split_rst.vt_array_mda.vt_array_rev.vt_assign_slice_overflow.vt_assoc.vt_assoc2.vt_assoc_wildcard_unsup.vt_bitsel_slice.vt_case_deep.vt_case_dupitems.vt_case_inside.vt_case_nest.vt_case_onehot.vt_case_reducer.vt_case_wild.vt_case_write1.vt_case_write2.vt_castdyn_enum.vt_chg_first.vt_clk_2in.vt_clk_dpulse.vt_clk_dsp.vt_clk_first.vt_clk_gater.vt_clk_latch.vt_clk_latchgate.vt_clk_powerdn.vt_clk_vecgen1.vt_concat_sel.vt_const_op_red_scope.vt_const_opt.vt_const_opt_cov.vt_const_opt_or.vt_const_opt_red.vt_const_opt_shortcut.vt_display_merge.vt_display_realtime.vt_display_wide.vt_dpi_var.vt_dynarray.vt_embed1.vt_emit_constw.vt_enum_large_methods.vt_enum_type_methods.vt_extend.vt_extend_class.vt_flag_compiler.vt_flag_csplit.vt_for_break.vt_for_funcbound.vt_for_local.vt_for_loop.vt_func_check.vt_func_endian.vt_func_first.vt_func_graphcirc.vt_func_noinl.vt_func_outfirst.vt_func_plog.vt_func_rand.vt_func_return.vt_func_sum.vt_gate_array.vt_gate_implicit.vt_gate_ormux.vt_gen_alw.vt_gen_assign.vt_gen_for.vt_gen_for0.vt_gen_for1.vt_gen_for_shuffle.vt_gen_forif.vt_gen_inc.vt_gen_intdot.vt_gen_intdot2.vt_gen_local.vt_gen_lsb.vt_gen_upscope.vt_if_deep.vt_iff.vt_inside_unpacked.vt_inside_wild.vt_inst_aport.vt_inst_array_partial.vt_inst_ccall.vt_inst_dff.vt_inst_mnpipe.vt_inst_notunsized.vt_inst_signed.vt_inst_signed1.vt_inst_slice.vt_interface_bind_public.vt_interface_dups.vt_interface_gen2.vt_interface_gen3.vt_interface_ref_trace.vt_math_clog2.vt_math_cmp.vt_math_concat0.v
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10
test_regress/t/t_EXAMPLE.v
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@ -22,7 +22,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -47,11 +47,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -63,7 +63,7 @@ module t(/*AUTOARG*/
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e

10
test_regress/t/t_alw_split_rst.v
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@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -44,11 +44,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -60,7 +60,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h77979747fd1b3a5a

10
test_regress/t/t_array_mda.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -26,11 +26,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -57,7 +57,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h619f75c3a6d948bd

2
test_regress/t/t_array_rev.v
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@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc=0;
integer cyc = 0;
// verilator lint_off LITENDIAN
logic arrd [0:1] = '{ 1'b1, 1'b0 };
// verilator lint_on LITENDIAN

2
test_regress/t/t_assign_slice_overflow.v
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@ -29,7 +29,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
// Non-constant offsets
reg varoffset1;
reg [6:0] varoffset2;

2
test_regress/t/t_assoc.v
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@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
integer i;

2
test_regress/t/t_assoc2.v
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@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
// associative array of an associative array
logic [31:0] a [logic [31:0]][logic [63:0]];

2
test_regress/t/t_assoc_wildcard_unsup.v
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@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
integer i;

10
test_regress/t/t_bitsel_slice.v
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@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdc21e42d85441511

10
test_regress/t/t_case_deep.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -42,11 +42,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -57,7 +57,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

10
test_regress/t/t_case_dupitems.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -52,7 +52,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

8
test_regress/t/t_case_inside.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -21,10 +21,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2);
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
@ -32,7 +32,7 @@ module t (/*AUTOARG*/
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

6
test_regress/t/t_case_nest.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -20,10 +20,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
if (cyc==1) begin
// Setup

10
test_regress/t/t_case_onehot.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5

10
test_regress/t/t_case_reducer.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38

6
test_regress/t/t_case_wild.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -20,9 +20,9 @@ module t (/*AUTOARG*/
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup

6
test_regress/t/t_case_write1.v
View File

@ -21,7 +21,7 @@ module t (/*AUTOARG*/
t_case_write1_tasks tasks ();
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
@ -30,9 +30,9 @@ module t (/*AUTOARG*/
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
//$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"});

6
test_regress/t/t_case_write2.v
View File

@ -21,7 +21,7 @@ module t (/*AUTOARG*/
t_case_write2_tasks tasks ();
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
@ -30,9 +30,9 @@ module t (/*AUTOARG*/
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
//$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"});

2
test_regress/t/t_castdyn_enum.v
View File

@ -36,7 +36,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
i = $cast(en, cyc);
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%0d en=%0d\n",$time, cyc, i, en);
$write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en);
`endif
cyc <= cyc + 1;
if (cyc == 10) begin

2
test_regress/t/t_chg_first.v
View File

@ -38,7 +38,7 @@ module t (/*AUTOARG*/
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
if (_mode==1) begin
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
//if (ord2 == 2 && ord7 != 7) $stop;
end
end

4
test_regress/t/t_clk_2in.v
View File

@ -85,7 +85,7 @@ module `t2 (
integer vn = 0;
integer vpn = 0;
task clear;
`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif
`ifdef TEST_VERBOSE $display("[%0t] clear\n", $time); `endif
p0 = 0;
p1 = 0;
p01 = 0;
@ -98,7 +98,7 @@ module `t2 (
endtask
`define display_counts(text) begin \
$write("[%0t] ",$time); \
$write("[%0t] ", $time); \
`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
$write(text); \
$write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \

2
test_regress/t/t_clk_dpulse.v
View File

@ -13,7 +13,7 @@ module t (/*AUTOARG*/
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg genclk;
// verilator lint_off MULTIDRIVEN
reg [7:0] set_both;

2
test_regress/t/t_clk_dsp.v
View File

@ -13,7 +13,7 @@ module t (/*AUTOARG*/
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg [7:0] padd;
reg dsp_ph1, dsp_ph2, dsp_reset;

2
test_regress/t/t_clk_first.v
View File

@ -72,7 +72,7 @@ module t_clk (/*AUTOARG*/
if (!_ranit) begin
_ranit <= 1;
`ifdef TEST_VERBOSE
$write("[%0t] t_clk: Running\n",$time);
$write("[%0t] t_clk: Running\n", $time);
`endif
reset_int_ <= 1;
end

10
test_regress/t/t_clk_gater.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
@ -55,7 +55,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;

2
test_regress/t/t_clk_latch.v
View File

@ -80,7 +80,7 @@ module t (/*AUTOARG*/
end
end
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
always @ (posedge fastclk) begin
cyc <= cyc+1;

8
test_regress/t/t_clk_latchgate.v
View File

@ -28,7 +28,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
@ -69,18 +69,18 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");

4
test_regress/t/t_clk_powerdn.v
View File

@ -58,10 +58,10 @@ module t (/*AUTOARG*/
end
end
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated);
$write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n", $time,reset_l,cyc,clkgate_e1f,count,countgated);
`endif
cyc <= cyc + 8'd1;
case (cyc)

10
test_regress/t/t_clk_vecgen1.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -33,11 +33,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -48,7 +48,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;

10
test_regress/t/t_concat_sel.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -45,11 +45,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -61,7 +61,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e

10
test_regress/t/t_const_op_red_scope.v
View File

@ -22,7 +22,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -81,11 +81,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -97,7 +97,7 @@ module t(/*AUTOARG*/
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h118c5809c7856d78

10
test_regress/t/t_const_opt.v
View File

@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,12 +37,12 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("o %b", o);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -54,7 +54,7 @@ module t(/*AUTOARG*/
else if (cyc < 99) begin
end
else begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha916d9291821c6e0

10
test_regress/t/t_const_opt_cov.v
View File

@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -38,11 +38,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -52,7 +52,7 @@ module t(/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha2601675a6ae4972

10
test_regress/t/t_const_opt_or.v
View File

@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -45,11 +45,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -59,7 +59,7 @@ module t(/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdc97b141ac5d6d7d

12
test_regress/t/t_const_opt_red.v
View File

@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -129,14 +129,14 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11);
$display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11);
$display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -174,12 +174,12 @@ module t(/*AUTOARG*/
if (z6 != '1) $stop;
if (z7 != '0) $stop;
if (match1_o != match2_o) begin
$write("[%0t] cyc==%0d m1=%d != m2=%d\n",$time, cyc, match1_o, match2_o);
$write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o);
$stop;
end
end
else begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h727fb78d09c1981e

10
test_regress/t/t_const_opt_shortcut.v
View File

@ -16,7 +16,7 @@ module t(/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -38,11 +38,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -52,7 +52,7 @@ module t(/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (import_func1() != 1) $stop; // this must be the first call
if (import_func3() != 1) $stop; // this must be the first call

24
test_regress/t/t_display_merge.v
View File

@ -23,14 +23,14 @@ module t (/*AUTOARG*/);
$write(" 1=%0d a=%m 1=%0d", one, one);
$display(" 1=%0d b=%m 1=%0d", one, one);
$display(" pre");
$display(" t=%0d",$time);
$display(" t2=%0d",$time);
$display(" t=%0d", $time);
$display(" t2=%0d", $time);
$display(" post");
$display(" t3=%0d",$time);
$display(" t4=%0d t5=%0d",$time,$time,$time);
$display(" t3=%0d", $time);
$display(" t4=%0d t5=%0d", $time,$time,$time);
$display("m");
$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
$display("mm");
$display("");
@ -38,14 +38,14 @@ module t (/*AUTOARG*/);
$write(" a=%m");
$write(" b=%m");
$write(" pre");
$write(" t=%0d",$time);
$write(" t2=%0d",$time);
$write(" t=%0d", $time);
$write(" t2=%0d", $time);
$write(" post");
$write(" t3=%0d",$time);
$write(" t4=%0d t5=%0d",$time,$time,$time);
$write(" t3=%0d", $time);
$write(" t4=%0d t5=%0d", $time,$time,$time);
$write("m");
$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
$display("mm");
$display("very very very very very very very very very very very very very very very very very very very very very very");

2
test_regress/t/t_display_realtime.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;

10
test_regress/t/t_display_wide.v
View File

@ -10,21 +10,21 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
$write("[%0t] cyc==%0d crc=%x%x%x%x\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");

8
test_regress/t/t_dpi_var.v
View File

@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
wire monclk = ~clk;
@ -25,7 +25,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n", $time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
@ -91,8 +91,8 @@ module sub (/*AUTOARG*/
$c("mon_class_name(this->name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
$c("mon_register_a(\"in\", &", in, ", false);");
$c("mon_register_a(\"fr_a\", &", fr_a, ", true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);

2
test_regress/t/t_dynarray.v
View File

@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
integer i;
string v;

8
test_regress/t/t_embed1.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -82,11 +82,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result,
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result,
got_vec_out, exp_vec_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -100,7 +100,7 @@ module t (/*AUTOARG*/
end
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
//Child prints this: $write("*-* All Finished *-*\n");
$finish;

10
test_regress/t/t_emit_constw.v
View File

@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -67,11 +67,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -147,7 +147,7 @@ module t (/*AUTOARG*/
w17 = w17 >>> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

2
test_regress/t/t_enum_large_methods.v
View File

@ -18,7 +18,7 @@ module t (/*AUTOARG*/
ELARGE = 'hf00d
} my_t;
integer cyc=0;
integer cyc = 0;
my_t e;
string all;

2
test_regress/t/t_enum_type_methods.v
View File

@ -19,7 +19,7 @@ module t (/*AUTOARG*/
E04 = 4
} my_t;
integer cyc=0;
integer cyc = 0;
my_t e;
int arrayfits [e.num]; // Check can use as constant

6
test_regress/t/t_extend.v
View File

@ -13,14 +13,14 @@ module t (/*AUTOARG*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
cyc <= cyc + 8'd1;
// coverage testing
if (one) begin end
@ -33,7 +33,7 @@ module t (/*AUTOARG*/
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
$c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");");
c_worked <= $c("this->my_function()");
c_wider <= $c9("0x10");
`else

6
test_regress/t/t_extend_class.v
View File

@ -10,14 +10,14 @@ module t (/*AUTOARG*/
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
cyc <= cyc+8'd1;
cyc <= cyc + 8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
@ -43,7 +43,7 @@ module t_extend_class_v (/*AUTOARG*/
always @* begin
// When "in" changes, call my method
out = $c("this->m_myobjp->my_math(",in,")");
out = $c("this->m_myobjp->my_math(", in, ")");
end
`systemc_header

4
test_regress/t/t_flag_compiler.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [89:0] in;
@ -33,7 +33,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
$write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin

4
test_regress/t/t_flag_csplit.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
parameter CNT = 5;
@ -36,7 +36,7 @@ module t (/*AUTOARG*/
else if (cyc==99) begin
`define EXPECTED_SUM 32'h1239
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d sum=%x\n",$time, cyc, w[CNT]);
$write("[%0t] cyc==%0d sum=%x\n", $time, cyc, w[CNT]);
`endif
if (w[CNT] !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

10
test_regress/t/t_for_break.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -32,11 +32,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -51,7 +51,7 @@ module t (/*AUTOARG*/
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0

2
test_regress/t/t_for_funcbound.v
View File

@ -22,7 +22,7 @@ module t (/*AUTOARG*/
reg [7:0] char;
integer loc;
begin
$write("[%0t] ",$time);
$write("[%0t] ", $time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);

4
test_regress/t/t_for_local.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg [31:0] loops;
reg [31:0] loops2;
@ -18,7 +18,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
$write("[%0t] t_loop: Running\n", $time);
// Unwind <
loops = 0;
loops2 = 0;

4
test_regress/t/t_for_loop.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg [31:0] loops;
reg [31:0] loops2;
@ -19,7 +19,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
$write("[%0t] t_loop: Running\n", $time);
// Unwind <
loops = 0;
loops2 = 0;

4
test_regress/t/t_func_check.v
View File

@ -10,7 +10,7 @@ module t (
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
@ -20,7 +20,7 @@ module t (
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end

10
test_regress/t/t_func_endian.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -39,11 +39,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -55,7 +55,7 @@ module t (/*AUTOARG*/
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h89522c3f5e5ca324) $stop;
$finish;

2
test_regress/t/t_func_first.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [7:0] cyc; initial cyc = 0;
reg set_in_task;
always @ (posedge clk) begin

2
test_regress/t/t_func_graphcirc.v
View File

@ -7,7 +7,7 @@
module t (clk);
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;

10
test_regress/t/t_func_noinl.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -39,11 +39,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

10
test_regress/t/t_func_outfirst.v
View File

@ -16,7 +16,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -43,11 +43,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -59,7 +59,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3a74e9d34771ad93

10
test_regress/t/t_func_plog.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg rst_n;
@ -41,11 +41,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
rst_n <= ~1'b0;
if (cyc==0) begin
// Setup
@ -60,7 +60,7 @@ module t (/*AUTOARG*/
if (pos1 !== pos2) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

2
test_regress/t/t_func_rand.v
View File

@ -20,7 +20,7 @@ module t (clk, Rand);
input [7:0] idx;
begin
`ifdef verilator
QxRand32 = $c("this->QxRandTbl(",tbl,",",idx,")");
QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")");
`else
QxRand32 = 32'hfeed0fad;
`endif

10
test_regress/t/t_func_return.v
View File

@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -31,11 +31,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -47,7 +47,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206

10
test_regress/t/t_func_sum.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -36,11 +36,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

10
test_regress/t/t_gate_array.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee

10
test_regress/t/t_gate_implicit.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a

12
test_regress/t/t_gate_ormux.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (rdata2 != rdata) $stop;
if (cyc==0) begin
// Setup
@ -52,13 +52,13 @@ module t (/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h8977713eb467bc86
if (sum !== `EXPECTED_SUM) $stop;
end
else if (cyc == `SIM_CYCLES) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
$write("*-* All Finished *-*\n");
$finish;
end

10
test_regress/t/t_gen_alw.v
View File

@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -29,11 +29,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -44,7 +44,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0

6
test_regress/t/t_gen_assign.v
View File

@ -12,7 +12,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [31:0] sum;
@ -27,10 +27,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;

4
test_regress/t/t_gen_for.v
View File

@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [7:0] crc;
genvar g;
@ -28,7 +28,7 @@ module t (/*AUTOARG*/
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n", $time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin

2
test_regress/t/t_gen_for0.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
Testit testit (/*AUTOINST*/
// Inputs

2
test_regress/t/t_gen_for1.v
View File

@ -12,7 +12,7 @@ module t (/*AUTOARG*/
wire b;
reg reset;
integer cyc=0;
integer cyc = 0;
Testit testit (/*AUTOINST*/
// Outputs

10
test_regress/t/t_gen_for_shuffle.v
View File

@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -33,11 +33,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -49,7 +49,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3e3a62edb61f8c7f

10
test_regress/t/t_gen_forif.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -29,12 +29,12 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
$write("[%0t] cyc==%0d crc=%x %x %x %x\n", $time, cyc, crc, Result, Result2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {56'h0, Result, Result2}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -46,7 +46,7 @@ module t (/*AUTOARG*/
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h4af37965592f64f9) $stop;
$finish;

2
test_regress/t/t_gen_inc.v
View File

@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
genvar g;
integer i;

4
test_regress/t/t_gen_intdot.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
wire out;
reg in;
@ -19,7 +19,7 @@ module t (/*AUTOARG*/
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
//$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup

4
test_regress/t/t_gen_intdot2.v
View File

@ -11,14 +11,14 @@ module t (/*AUTOARG*/
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
//$write("[%0t] cyc==%0d %x %x\n", $time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup

2
test_regress/t/t_gen_local.v
View File

@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
localparam N = 31;

10
test_regress/t/t_gen_lsb.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3db7bc8bfe61f983

2
test_regress/t/t_gen_upscope.v
View File

@ -36,7 +36,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
integer cyc=0;
integer cyc = 0;
tag tag ();
b b ();

10
test_regress/t/t_if_deep.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

10
test_regress/t/t_iff.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -23,11 +23,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -39,7 +39,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'he58508de5310b541

2
test_regress/t/t_inside_unpacked.v
View File

@ -22,7 +22,7 @@ module t(/*AUTOARG*/
if (MISS_INSIDE != 0) $stop;
end
integer cyc=0;
integer cyc = 0;
int array [10];
logic l;

10
test_regress/t/t_inside_wild.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3

10
test_regress/t/t_inst_aport.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e

10
test_regress/t/t_inst_array_partial.v
View File

@ -43,7 +43,7 @@ module t (/*AUTOARG*/
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -55,11 +55,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -71,7 +71,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6

4
test_regress/t/t_inst_ccall.v
View File

@ -46,8 +46,8 @@ endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
assign longout = $c32("(",narrow,"+1)");
assign quadout = $c64("(",quad,"+1)");
assign longout = $c32("(", narrow, "+1)");
assign quadout = $c64("(", quad, "+1)");
`else
assign longout = narrow + 8'd1;
assign quadout = quad + 64'd1;

10
test_regress/t/t_inst_dff.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -42,11 +42,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -64,7 +64,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hbcfcebdb75ec9d32

4
test_regress/t/t_inst_mnpipe.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [2:0] sum;
@ -20,7 +20,7 @@ module t (/*AUTOARG*/
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
//$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin

10
test_regress/t/t_inst_notunsized.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1

2
test_regress/t/t_inst_signed.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
wire signed [7:0] sgn_wide;
wire [7:0] unsgn_wide;

2
test_regress/t/t_inst_signed1.v
View File

@ -14,7 +14,7 @@ module t (/*AUTOARG*/
wire signed o1;
wire signed o2;
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
sub1 sub1 (.i(i), .o(o1));
sub2 sub2 (.i(o1), .o(o2));

10
test_regress/t/t_inst_slice.v
View File

@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -31,11 +31,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum);
$write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -47,7 +47,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb42b2f48a0a9375a

2
test_regress/t/t_interface_bind_public.v
View File

@ -44,7 +44,7 @@ module t
.io_success(success)
);
integer cyc=0;
integer cyc = 0;
always @ (posedge clk) begin
cyc = cyc + 1;

10
test_regress/t/t_interface_dups.v
View File

@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -57,11 +57,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -73,7 +73,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h6fd1bead9df31b07

2
test_regress/t/t_interface_gen2.v
View File

@ -24,7 +24,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo);
$write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];

2
test_regress/t/t_interface_gen3.v
View File

@ -24,7 +24,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo);
$write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];

2
test_regress/t/t_interface_ref_trace.v
View File

@ -23,7 +23,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
ifc intf_1(.*);
ifc intf_2(.*);

10
test_regress/t/t_math_clog2.v
View File

@ -16,7 +16,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
crc <= 64'h0;
if (`CLOG2(32'h0) != 0) $stop;
@ -82,7 +82,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hcbc77bb9b3784ea0) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");

4
test_regress/t/t_math_cmp.v
View File

@ -50,7 +50,7 @@ module t (/*AUTOARG*/
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
integer cyc; initial cyc = 0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
@ -117,7 +117,7 @@ module prover (
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
integer cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin

10
test_regress/t/t_math_concat0.v
View File

@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h09be74b1b0f8c35d

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