forked from github/verilator
151 lines
4.2 KiB
Systemverilog
151 lines
4.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [15:0] l;
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reg [49:0] q;
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reg [79:0] w;
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int lc;
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reg lo;
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reg l0;
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int qc;
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reg qo;
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reg q0;
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int wc;
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reg wo;
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reg w0;
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always @* begin
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lc = $countones(l);
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lo = $onehot(l);
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l0 = $onehot0(l);
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wc = $countones(w);
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wo = $onehot(w);
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w0 = $onehot0(w);
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qc = $countones(q);
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qo = $onehot(q);
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q0 = $onehot0(q);
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end
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integer cyc; initial cyc=1;
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integer cyc_com;
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always_comb begin
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cyc_com = cyc;
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end
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integer cyc_d1;
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always_ff @ (posedge clk) begin
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cyc_d1 <= cyc_com;
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end
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initial begin
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// Constification check
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if ($countones(32'b11001011101) != 7) $stop;
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if ($countones(32'b0) != 0) $stop;
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if ($isunknown(32'b11101x11111) != 1) $stop;
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if ($isunknown(32'b11101011111) != 0) $stop;
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if ($isunknown(32'b10zzzzzzzzz) != 1) $stop;
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if ($bits(0) != 32'd32) $stop;
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if ($bits(lc) != 32) $stop;
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if ($onehot(32'b00000001000000) != 1'b1) $stop;
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if ($onehot(32'b00001001000000) != 1'b0) $stop;
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if ($onehot(32'b0) != 1'b0) $stop;
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if ($onehot0(32'b00000001000000) != 1'b1) $stop;
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if ($onehot0(32'b00001001000000) != 1'b0) $stop;
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if ($onehot0(32'b0) != 1'b1) $stop;
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
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// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
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if (cyc_com != cyc_com) $stop;
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if (cyc_d1 != cyc-1) $stop;
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if (cyc==1) begin
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l <= 16'b0;
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q <= 50'h0;
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w <= 80'h0;
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end
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if (cyc==2) begin
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l <= ~16'b0;
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q <= ~50'h0;
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w <= ~80'h0;
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//
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if ({lc,lo,l0} != {32'd0,1'b0,1'b1}) $stop;
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if ({qc,qo,q0} != {32'd0,1'b0,1'b1}) $stop;
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if ({wc,wo,w0} != {32'd0,1'b0,1'b1}) $stop;
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end
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if (cyc==3) begin
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l <= 16'b0010110010110111;
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q <= 50'h01_1111_0001;
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w <= 80'h0100_0000_0f00_00f0_0000;
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//
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if ({lc,lo,l0} != {32'd16,1'b0,1'b0}) $stop;
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if ({qc,qo,q0} != {32'd50,1'b0,1'b0}) $stop;
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if ({wc,wo,w0} != {32'd80,1'b0,1'b0}) $stop;
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end
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if (cyc==4) begin
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l <= 16'b0000010000000000;
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q <= 50'h1_0000_0000;
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w <= 80'h010_00000000_00000000;
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//
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if ({lc,lo,l0} != {32'd9,1'b0,1'b0}) $stop;
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if ({qc,qo,q0} != {32'd6,1'b0,1'b0}) $stop;
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if ({wc,wo,w0} != {32'd9,1'b0,1'b0}) $stop;
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end
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if (cyc==5) begin
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l <= 16'b0000000100000000;
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q <= 50'h8000_0000_0000;
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w <= 80'h10_00000000_00000000;
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//
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if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop;
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if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop;
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if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop;
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end
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if (cyc==6) begin
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l <= 16'b0000100100000000;
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q <= 50'h01_00000100;
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w <= 80'h01_00000100_00000000;
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//
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if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop;
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if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop;
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if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop;
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end
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if (cyc==7) begin
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//
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if ({lc,lo,l0} != {32'd2,1'b0,1'b0}) $stop;
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if ({qc,qo,q0} != {32'd2,1'b0,1'b0}) $stop;
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if ({wc,wo,w0} != {32'd2,1'b0,1'b0}) $stop;
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end
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if (cyc==8) begin
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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initial begin
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if ($isunknown(4'b000x) !== 1'b1) $stop;
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if ($isunknown(4'b000z) !== 1'b1) $stop;
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if ($isunknown(4'b00xz) !== 1'b1) $stop;
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if ($isunknown(4'b0000) !== 1'b0) $stop;
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end
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final begin
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$write("Goodbye world, at cycle %0d\n", cyc);
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end
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endmodule
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