forked from github/verilator
144 lines
4.3 KiB
Systemverilog
144 lines
4.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2011 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off SHORTREAL
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integer i;
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reg [63:0] b;
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shortreal r, r2;
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integer cyc = 0;
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realtime uninit;
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initial if (uninit != 0.0) $stop;
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initial begin
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if (1_00_0.0_1 != 1000.01) $stop;
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// rtoi truncates
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if ($rtoi(36.7) != 36) $stop;
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if ($rtoi(36.5) != 36) $stop;
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if ($rtoi(36.4) != 36) $stop;
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// casting rounds
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if ((integer '(36.7)) != 37) $stop;
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if ((integer '(36.5)) != 37) $stop;
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if ((integer '(36.4)) != 36) $stop;
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// assignment rounds
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// verilator lint_off REALCVT
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i = 36.7; if (i != 37) $stop;
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i = 36.5; if (i != 37) $stop;
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i = 36.4; if (i != 36) $stop;
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r = 10'd38; if (r!=38.0) $stop;
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// verilator lint_on REALCVT
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// operators
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if ((-(1.5)) != -1.5) $stop;
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if ((+(1.5)) != 1.5) $stop;
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if (((1.5)+(1.25)) != 2.75) $stop;
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if (((1.5)-(1.25)) != 0.25) $stop;
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if (((1.5)*(1.25)) != 1.875) $stop;
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if (((1.5)/(1.25)) != 1.2) $stop;
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//
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if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
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if (((1.5)!=(2)) != 1'b1) $stop;
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if (((1.5)> (2)) != 1'b0) $stop;
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if (((1.5)>=(2)) != 1'b0) $stop;
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if (((1.5)< (2)) != 1'b1) $stop;
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if (((1.5)<=(2)) != 1'b1) $stop;
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if (((1.5)==(1.5)) != 1'b1) $stop;
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if (((1.5)!=(1.5)) != 1'b0) $stop;
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if (((1.5)> (1.5)) != 1'b0) $stop;
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if (((1.5)>=(1.5)) != 1'b1) $stop;
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if (((1.5)< (1.5)) != 1'b0) $stop;
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if (((1.5)<=(1.5)) != 1'b1) $stop;
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if (((1.6)==(1.5)) != 1'b0) $stop;
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if (((1.6)!=(1.5)) != 1'b1) $stop;
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if (((1.6)> (1.5)) != 1'b1) $stop;
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if (((1.6)>=(1.5)) != 1'b1) $stop;
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if (((1.6)< (1.5)) != 1'b0) $stop;
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if (((1.6)<=(1.5)) != 1'b0) $stop;
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//
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if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
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if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
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//
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if (!1.7) $stop;
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if (!(!0.0)) $stop;
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if (1.8 && 0.0) $stop;
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if (!(1.8 || 0.0)) $stop;
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//
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i=0;
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for (r=1.0; r<2.0; r=r+0.1) i++;
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if (i!=10) $stop;
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// bug
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r = $bitstoshortreal($shortrealtobits(1.414));
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if (r != 1.414) $stop;
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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end
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else if (cyc<90) begin
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if ($time != {32'h0, $rtoi($realtime)}) $stop;
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if ($itor(cyc) != cyc) $stop;
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//Unsup: if ((real `($time)) != $realtime) $stop;
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r = $itor(cyc*2);
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i = $rtoi(r);
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if (i!=cyc*2) $stop;
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//
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r = $itor(cyc)/1.5;
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b = $realtobits(r);
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r2 = $bitstoreal(b);
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if (r != r2) $stop;
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//
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// Trust the integer math as a comparison
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r = $itor(cyc);
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if ($rtoi(-r) != -cyc) $stop;
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if ($rtoi(+r) != cyc) $stop;
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if ($rtoi(r+2.0) != (cyc+2)) $stop;
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if ($rtoi(r-2.0) != (cyc-2)) $stop;
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if ($rtoi(r*2.0) != (cyc*2)) $stop;
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if ($rtoi(r/2.0) != (cyc/2)) $stop;
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r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
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//
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r2 = $itor(cyc);
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case (r)
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(r2-1.0): $stop;
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r2: ;
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default: $stop;
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endcase
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//
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r = $itor(cyc);
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if ((r==50.0) != (cyc==50)) $stop;
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if ((r!=50.0) != (cyc!=50)) $stop;
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if ((r> 50.0) != (cyc> 50)) $stop;
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if ((r>=50.0) != (cyc>=50)) $stop;
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if ((r< 50.0) != (cyc< 50)) $stop;
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if ((r<=50.0) != (cyc<=50)) $stop;
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//
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if ($rtoi((r-50.0) ? 10.0 : 20.0)
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!= (((cyc-50)!=0) ? 10 : 20)) $stop;
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//
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if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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