forked from github/verilator
102 lines
2.9 KiB
Systemverilog
102 lines
2.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2011 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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real r;
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reg [31:0] v32;
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reg [63:0] v64;
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reg [95:0] v96;
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initial begin
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// verilator lint_off REALCVT
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v32 = -1.5;
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v64 = -1.5;
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v96 = -1.5;
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// verilator lint_on REALCVT
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`checkh(v32, 32'hfffffffe);
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`checkh(v64, 64'hfffffffffffffffe);
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`checkh(v96, 96'hfffffffffffffffffffffffe);
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// verilator lint_off REALCVT
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v32 = 12456789012345678912345.5;
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v64 = 12456789012345678912345.5;
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v96 = 12456789012345678912345.5;
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// verilator lint_on REALCVT
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`checkh(v32, 32'he5400000);
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`checkh(v64, 64'h48acb7d4e5400000);
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`checkh(v96, 96'h000002a348acb7d4e5400000);
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// verilator lint_off REALCVT
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v32 = -12456789012345678912345.5;
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v64 = -12456789012345678912345.5;
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v96 = -12456789012345678912345.5;
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// verilator lint_on REALCVT
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`checkh(v32, 32'h1ac00000);
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`checkh(v64, 64'hb753482b1ac00000);
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`checkh(v96, 96'hfffffd5cb753482b1ac00000);
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end
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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r <= 0;
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end
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else if (cyc == 11) begin
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// verilator lint_off REALCVT
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v32 = r;
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v64 = r;
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v96 = r;
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// verilator lint_on REALCVT
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`checkh(v32, '0);
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`checkh(v64, '0);
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`checkh(v96, '0);
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end
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else if (cyc == 20) begin
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r <= -5.24567;
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end
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else if (cyc == 21) begin
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// verilator lint_off REALCVT
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v32 = r;
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v64 = r;
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v96 = r;
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// verilator lint_on REALCVT
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`checkh(v32, 32'hfffffffb);
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`checkh(v64, 64'hfffffffffffffffb);
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`checkh(v96, 96'hfffffffffffffffffffffffb);
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end
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else if (cyc == 30) begin
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r <= 12456789012345678912345.5;
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end
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else if (cyc == 31) begin
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// verilator lint_off REALCVT
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v32 = r;
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v64 = r;
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v96 = r;
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// verilator lint_on REALCVT
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`checkh(v32, 32'he5400000);
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`checkh(v64, 64'h48acb7d4e5400000);
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`checkh(v96, 96'h000002a348acb7d4e5400000);
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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