forked from github/verilator
8 lines
516 B
Plaintext
8 lines
516 B
Plaintext
%Warning-WIDTHTRUNC: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
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: ... In instance t.sub3
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18 | wire [0:0] b = a;
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| ^
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... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
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... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
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%Error: Exiting due to
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