forked from github/verilator
Split WIDTH warning into WIDTHEXPAND and WIDTHTRUNC (#3900)
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@ -1,4 +1,4 @@
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.. comment: generated by t_lint_width_docs_bad
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.. comment: generated by t_lint_widthexpand_docs_bad
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.. code-block:: sv
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:linenos:
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:emphasize-lines: 3
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@ -1,4 +1,4 @@
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.. comment: generated by t_lint_width_docs_bad
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.. comment: generated by t_lint_widthexpand_docs_bad
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.. code-block:: sv
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:emphasize-lines: 1
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4
docs/gen/ex_WIDTHEXPAND_1_msg.rst
Normal file
4
docs/gen/ex_WIDTHEXPAND_1_msg.rst
Normal file
@ -0,0 +1,4 @@
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.. comment: generated by t_lint_widthexpand_docs_bad
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.. code-block::
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%Warning-WIDTHEXPAND: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits.
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@ -1,4 +0,0 @@
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.. comment: generated by t_lint_width_docs_bad
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.. code-block::
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%Warning-WIDTH: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits.
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@ -1790,16 +1790,27 @@ List Of Warnings
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For example, this is a missized index:
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.. include:: ../../docs/gen/ex_WIDTH_1_faulty.rst
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.. include:: ../../docs/gen/ex_WIDTHEXPAND_1_faulty.rst
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Results in:
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Results in a WIDTHEXPAND warning:
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.. include:: ../../docs/gen/ex_WIDTH_1_msg.rst
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.. include:: ../../docs/gen/ex_WIDTHEXPAND_1_msg.rst
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One possible fix:
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.. include:: ../../docs/gen/ex_WIDTH_1_fixed.rst
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.. include:: ../../docs/gen/ex_WIDTHEXPAND_1_fixed.rst
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.. option:: WIDTHTRUNC
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A more granular WIDTH warning, for when a value is truncated
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.. option:: WIDTHEXPAND
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A more granular WIDTH warning, for when a value is zero expanded
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.. option:: WIDTHXZEXPAND
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A more granular WIDTH warning, for when a value is xz expanded
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.. option:: WIDTHCONCAT
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@ -332,8 +332,7 @@ public:
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}
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bool waive(V3ErrorCode code, const string& match) {
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for (const auto& itr : m_waivers) {
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if (((itr.first == code) || (itr.first == V3ErrorCode::I_LINT)
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|| (code.unusedError() && itr.first == V3ErrorCode::I_UNUSED))
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if ((code.isUnder(itr.first) || (itr.first == V3ErrorCode::I_LINT))
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&& VString::wildmatch(match, itr.second)) {
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return true;
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}
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@ -262,7 +262,7 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const
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}
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if (argp->widthMin() > 8 && fmtLetter == 'c') {
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// Technically legal, but surely not what the user intended.
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argp->v3warn(WIDTH, dispp->verilogKwd() << "of %c format of > 8 bit value");
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argp->v3warn(WIDTHTRUNC, dispp->verilogKwd() << "of %c format of > 8 bit value");
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}
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}
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// string pfmt = "%"+displayFormat(argp, vfmt, fmtLetter)+fmtLetter;
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@ -147,6 +147,9 @@ public:
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VARHIDDEN, // Hiding variable
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WAITCONST, // Wait condition is constant
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WIDTH, // Width mismatch
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WIDTHTRUNC, // Width mismatch- lhs < rhs
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WIDTHEXPAND, // Width mismatch- lhs > rhs
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WIDTHXZEXPAND, // Width mismatch- lhs > rhs xz filled
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WIDTHCONCAT, // Unsized numbers/parameters in concatenations
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ZERODLY, // #0 delay
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_ENUM_MAX
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@ -192,7 +195,7 @@ public:
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"UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS",
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"UNPACKED", "UNSIGNED", "UNUSEDGENVAR", "UNUSEDPARAM", "UNUSEDSIGNAL",
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"USERERROR", "USERFATAL", "USERINFO", "USERWARN",
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"VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHCONCAT", "ZERODLY",
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"VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHTRUNC", "WIDTHEXPAND", "WIDTHXZEXPAND", "WIDTHCONCAT", "ZERODLY",
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" MAX"
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};
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// clang-format on
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@ -223,7 +226,8 @@ public:
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|| m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST
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|| m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT || m_e == IMPLICITSTATIC
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|| m_e == LATCH || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT
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|| m_e == UNSIGNED || m_e == WIDTH);
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|| m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC || m_e == WIDTHEXPAND
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|| m_e == WIDTHXZEXPAND);
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}
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// Warnings that are style only
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bool styleError() const VL_MT_SAFE {
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@ -238,6 +242,20 @@ public:
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bool unusedError() const VL_MT_SAFE {
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return (m_e == UNUSEDGENVAR || m_e == UNUSEDPARAM || m_e == UNUSEDSIGNAL);
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}
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bool isUnder(V3ErrorCode other) {
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// backwards compatibility inheritance-like warnings
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if (m_e == other) { return true; }
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if (other == V3ErrorCode::WIDTH) {
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return (m_e == WIDTH || m_e == WIDTHEXPAND || m_e == WIDTHTRUNC
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|| m_e == WIDTHXZEXPAND);
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}
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if (other == V3ErrorCode::I_UNUSED) {
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return (m_e == UNUSEDGENVAR || m_e == UNUSEDPARAM || m_e == UNUSEDSIGNAL);
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}
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return false;
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}
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static bool unusedMsg(const char* msgp) { return 0 == VL_STRCASECMP(msgp, "UNUSED"); }
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};
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constexpr bool operator==(const V3ErrorCode& lhs, const V3ErrorCode& rhs) {
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@ -307,7 +325,14 @@ public:
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}
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static void abortIfWarnings();
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static void suppressThisWarning(); // Suppress next %Warn if user has it off
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static void pretendError(V3ErrorCode code, bool flag) { s_pretendError[code] = flag; }
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static void pretendError(V3ErrorCode code, bool flag) {
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if (code == V3ErrorCode::WIDTH) {
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s_pretendError[V3ErrorCode::WIDTHTRUNC] = flag;
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s_pretendError[V3ErrorCode::WIDTHEXPAND] = flag;
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s_pretendError[V3ErrorCode::WIDTHXZEXPAND] = flag;
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}
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s_pretendError[code] = flag;
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}
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static bool isError(V3ErrorCode code, bool supp);
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static string lineStr(const char* filename, int lineno);
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static V3ErrorCode errorCode() VL_MT_SAFE { return s_errorCode; }
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@ -350,6 +375,7 @@ inline void v3errorEndFatal(std::ostringstream& sstr) {
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// evaluation order as otherwise we couldn't ensure v3errorPrep is called first.
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#define v3warnCode(code, msg) \
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v3errorEnd((V3Error::v3errorPrep(code), (V3Error::v3errorStr() << msg), V3Error::v3errorStr()))
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#define v3warnCodeFatal(code, msg) \
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v3errorEndFatal( \
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(V3Error::v3errorPrep(code), (V3Error::v3errorStr() << msg), V3Error::v3errorStr()))
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@ -261,6 +261,11 @@ public:
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// Turn on/off warning messages on this line.
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void warnOn(V3ErrorCode code, bool flag) {
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if (code == V3ErrorCode::WIDTH) {
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warnOn(V3ErrorCode::WIDTHTRUNC, flag);
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warnOn(V3ErrorCode::WIDTHEXPAND, flag);
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warnOn(V3ErrorCode::WIDTHXZEXPAND, flag);
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}
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m_msgEnIdx = singleton().msgEnSetBit(m_msgEnIdx, code, flag);
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}
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void warnOff(V3ErrorCode code, bool flag) { warnOn(code, !flag); }
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@ -703,7 +703,8 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
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return str;
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} // case b/d/x/o
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case 'c': {
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if (width() > 8) fl->v3warn(WIDTH, "$display-like format of %c format of > 8 bit value");
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if (width() > 8)
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fl->v3warn(WIDTHTRUNC, "$display-like format of %c format of > 8 bit value");
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const unsigned int v = bitsValue(0, 8);
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char strc[2];
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strc[0] = v & 0xff;
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@ -2243,7 +2244,8 @@ void V3Number::opCleanThis(bool warnOnTruncation) {
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const uint32_t newValueXMsb = v.m_valueX & hiWordMask();
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if (warnOnTruncation && (newValueMsb != v.m_value || newValueXMsb != v.m_valueX)) {
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// Displaying in decimal avoids hiWordMask truncation
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v3warn(WIDTH, "Value too large for " << width() << " bit number: " << displayed("%d"));
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v3warn(WIDTHTRUNC,
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"Value too large for " << width() << " bit number: " << displayed("%d"));
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}
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m_data.num()[words() - 1] = {newValueMsb, newValueXMsb};
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}
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@ -1564,6 +1564,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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});
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DECL_OPTION("-Wno-style", CbCall, []() { FileLine::globalWarnStyleOff(true); });
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DECL_OPTION("-Wno-UNUSED", CbCall, []() { FileLine::globalWarnUnusedOff(true); });
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DECL_OPTION("-Wno-WIDTH", CbCall, []() { FileLine::globalWarnOff(V3ErrorCode::WIDTH, true); });
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DECL_OPTION("-Wwarn-", CbPartialMatch, [this, fl, &parser](const char* optp) {
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const V3ErrorCode code{optp};
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if (code == V3ErrorCode::EC_ERROR) {
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@ -1585,6 +1586,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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V3Error::pretendError(V3ErrorCode::UNUSEDSIGNAL, false);
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V3Error::pretendError(V3ErrorCode::UNUSEDPARAM, false);
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});
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DECL_OPTION("-Wwarn-WIDTH", CbCall, []() {
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FileLine::globalWarnOff(V3ErrorCode::WIDTH, false);
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V3Error::pretendError(V3ErrorCode::WIDTH, false);
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});
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DECL_OPTION("-waiver-output", Set, &m_waiverOutput);
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DECL_OPTION("-x-assign", CbVal, [this, fl](const char* valp) {
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@ -118,6 +118,12 @@ std::ostream& operator<<(std::ostream& str, const Castable& rhs) {
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return str << s_det[rhs];
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}
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#define v3widthWarn(lhs, rhs, msg) \
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v3errorEnd((V3Error::v3errorPrep((lhs) < (rhs) ? V3ErrorCode::WIDTHTRUNC \
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: (lhs) > (rhs) ? V3ErrorCode::WIDTHEXPAND \
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: V3ErrorCode::WIDTH), \
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(V3Error::v3errorStr() << msg), V3Error::v3errorStr()))
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//######################################################################
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// Width state, as a visitor of each AstNode
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@ -910,15 +916,16 @@ private:
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userIterateAndNext(nodep->lsbp(), WidthVP{SELF, FINAL}.p());
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if (widthBad(nodep->lsbp(), selwidthDTypep) && nodep->lsbp()->width() != 32) {
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if (!nodep->fileline()->warnIsOff(V3ErrorCode::WIDTH)) {
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nodep->v3warn(WIDTH,
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"Bit extraction of var["
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<< (frommsb / elw) << ":" << (fromlsb / elw) << "] requires "
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<< (selwidth / elw) << " bit index, not "
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<< (nodep->lsbp()->width() / elw)
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<< (nodep->lsbp()->width() != nodep->lsbp()->widthMin()
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? " or " + cvtToStr(nodep->lsbp()->widthMin() / elw)
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: "")
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<< " bits.");
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nodep->v3widthWarn(
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(selwidth / elw), (nodep->lsbp()->width() / elw),
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"Bit extraction of var["
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<< (frommsb / elw) << ":" << (fromlsb / elw) << "] requires "
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<< (selwidth / elw) << " bit index, not "
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<< (nodep->lsbp()->width() / elw)
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<< (nodep->lsbp()->width() != nodep->lsbp()->widthMin()
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? " or " + cvtToStr(nodep->lsbp()->widthMin() / elw)
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: "")
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<< " bits.");
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UINFO(1, " Related node: " << nodep << endl);
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}
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}
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@ -988,13 +995,14 @@ private:
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AstNodeDType* const selwidthDTypep
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= nodep->findLogicDType(selwidth, selwidth, nodep->bitp()->dtypep()->numeric());
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if (widthBad(nodep->bitp(), selwidthDTypep) && nodep->bitp()->width() != 32) {
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nodep->v3warn(WIDTH, "Bit extraction of array["
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<< frommsb << ":" << fromlsb << "] requires " << selwidth
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<< " bit index, not " << nodep->bitp()->width()
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<< (nodep->bitp()->width() != nodep->bitp()->widthMin()
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? " or " + cvtToStr(nodep->bitp()->widthMin())
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: "")
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<< " bits.");
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nodep->v3widthWarn(selwidth, nodep->bitp()->width(),
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"Bit extraction of array["
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<< frommsb << ":" << fromlsb << "] requires " << selwidth
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<< " bit index, not " << nodep->bitp()->width()
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<< (nodep->bitp()->width() != nodep->bitp()->widthMin()
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? " or " + cvtToStr(nodep->bitp()->widthMin())
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: "")
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<< " bits.");
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if (!nodep->fileline()->warnIsOff(V3ErrorCode::WIDTH)) {
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UINFO(1, " Related node: " << nodep << endl);
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UINFO(1, " Related dtype: " << nodep->dtypep() << endl);
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@ -6077,8 +6085,9 @@ private:
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else if (!constp->num().sized()
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// Make it the proper size. Careful of proper extension of 0's/1's
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&& expWidth > 32 && constp->num().isMsbXZ()) {
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constp->v3warn(WIDTH, "Unsized constant being X/Z extended to "
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<< expWidth << " bits: " << constp->prettyName());
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constp->v3warn(WIDTHXZEXPAND, "Unsized constant being X/Z extended to "
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<< expWidth
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<< " bits: " << constp->prettyName());
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V3Number num(constp, expWidth);
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num.opExtendXZ(constp->num(), constp->width());
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AstNodeExpr* const newp = new AstConst{constp->fileline(), num};
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@ -6266,15 +6275,16 @@ private:
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if (bad) {
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{ // if (warnOn), but not needed here
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if (debug() > 4) nodep->backp()->dumpTree("- back: ");
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nodep->v3warn(WIDTH, "Logical operator "
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<< nodep->prettyTypeName() << " expects 1 bit on the "
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<< side << ", but " << side << "'s "
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<< underp->prettyTypeName() << " generates "
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<< underp->width()
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<< (underp->width() != underp->widthMin()
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? " or " + cvtToStr(underp->widthMin())
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: "")
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<< " bits.");
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nodep->v3widthWarn(1, underp->width(),
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"Logical operator "
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<< nodep->prettyTypeName() << " expects 1 bit on the "
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<< side << ", but " << side << "'s "
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<< underp->prettyTypeName() << " generates "
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<< underp->width()
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<< (underp->width() != underp->widthMin()
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? " or " + cvtToStr(underp->widthMin())
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: "")
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<< " bits.");
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}
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VL_DO_DANGLING(fixWidthReduce(VN_AS(underp, NodeExpr)), underp); // Changed
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}
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@ -6448,16 +6458,18 @@ private:
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}
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if (bad && warnOn) {
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if (debug() > 4) nodep->backp()->dumpTree("- back: ");
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nodep->v3warn(
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WIDTH, ucfirst(nodep->prettyOperatorName())
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<< " expects " << expWidth
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<< (expWidth != expWidthMin ? " or " + cvtToStr(expWidthMin) : "")
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<< " bits on the " << side << ", but " << side << "'s "
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<< underp->prettyTypeName() << " generates " << underp->width()
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<< (underp->width() != underp->widthMin()
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? " or " + cvtToStr(underp->widthMin())
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: "")
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<< " bits.");
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nodep->v3widthWarn(
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expWidth, underp->width(),
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ucfirst(nodep->prettyOperatorName())
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<< " expects " << expWidth
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<< (expWidth != expWidthMin ? " or " + cvtToStr(expWidthMin) : "")
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<< " bits on the " << side << ", but " << side << "'s "
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<< underp->prettyTypeName() << " generates " << underp->width()
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<< (underp->width() != underp->widthMin()
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? " or " + cvtToStr(underp->widthMin())
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: "")
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<< " bits.");
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}
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if (bad || underp->width() != expWidth) {
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// If we're in an NodeAssign, don't truncate the RHS if the LHS is
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@ -2,10 +2,10 @@
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: ... In instance t
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38 | test_out <= '{'0, '0};
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| ^~
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%Warning-WIDTH: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
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: ... In instance t
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%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
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: ... In instance t
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38 | test_out <= '{'0, '0};
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| ^~
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... For warning description see https://verilator.org/warn/WIDTH?v=latest
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
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... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
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%Error: Exiting due to
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@ -3,10 +3,10 @@
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: ... Suggested alternative: 'memb2'
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18 | c.memb3 = 3;
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| ^~~~~
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%Warning-WIDTH: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits.
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: ... In instance t
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%Warning-WIDTHTRUNC: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits.
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: ... In instance t
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18 | c.memb3 = 3;
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| ^
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... For warning description see https://verilator.org/warn/WIDTH?v=latest
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
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... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
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%Error: Exiting due to
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@ -1,15 +1,15 @@
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%Warning-WIDTH: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
||||
: ... In instance t
|
||||
%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
||||
: ... In instance t
|
||||
13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop;
|
||||
| ^~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTH: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTHXZEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHXZEXPAND */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
|
||||
: ... In instance t
|
||||
14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop;
|
||||
| ^~~
|
||||
%Warning-WIDTH: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
|
||||
: ... In instance t
|
||||
%Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
|
||||
: ... In instance t
|
||||
15 | if (68'h?_????????_???????? !== 'd?) $stop;
|
||||
| ^~~
|
||||
%Error: Exiting due to
|
||||
|
@ -1,6 +1,6 @@
|
||||
%Warning-WIDTH: t/t_display_cwide_bad.v:10:7: $display-like format of %c format of > 8 bit value
|
||||
%Warning-WIDTHTRUNC: t/t_display_cwide_bad.v:10:7: $display-like format of %c format of > 8 bit value
|
||||
10 | $display("%c", 32'h1234);
|
||||
| ^~~~~~~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -3,11 +3,11 @@
|
||||
21 | import_func0(sig0);
|
||||
| ^~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Warning-WIDTH: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits.
|
||||
: ... In instance t
|
||||
21 | import_func0(sig0);
|
||||
| ^~~~~~~~~~~~
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:23:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2]')
|
||||
: ... In instance t
|
||||
23 | import_func1(sig1);
|
||||
@ -24,8 +24,8 @@
|
||||
: ... In instance t
|
||||
29 | import_func0(sig0[1]);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_dpi_unpack_bad.v:29:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:29:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits.
|
||||
: ... In instance t
|
||||
29 | import_func0(sig0[1]);
|
||||
| ^~~~~~~~~~~~
|
||||
%Error: Exiting due to
|
||||
|
@ -1,9 +1,9 @@
|
||||
%Warning-WIDTH: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits.
|
||||
: ... In instance t
|
||||
15 | a = new [s];
|
||||
| ^~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str""
|
||||
15 | a = new [s];
|
||||
| ^
|
||||
|
@ -1,7 +1,7 @@
|
||||
%Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHTRUNC: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Warning-UNUSEDSIGNAL: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo'
|
||||
: ... In instance t
|
||||
%Error: Exiting due to
|
||||
|
@ -1,7 +1,7 @@
|
||||
%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
||||
: ... In instance t
|
||||
10 | wire [3:0] foo = 6'h2e;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,6 +1,7 @@
|
||||
%Error-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
||||
: ... In instance t
|
||||
10 | wire [3:0] foo = 6'h2e;
|
||||
| ^
|
||||
... For error description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,6 +1,6 @@
|
||||
%Warning-WIDTH: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
||||
: ... In instance t
|
||||
10 | wire [3:0] foo = 6'h2e;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
|
@ -1,11 +1,11 @@
|
||||
%Warning-WIDTH: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits.
|
||||
: ... In instance t
|
||||
13 | out = MUX (in);
|
||||
| ^~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTH: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits.
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHTRUNC: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits.
|
||||
: ... In instance t
|
||||
13 | out = MUX (in);
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
@ -1,19 +1,19 @@
|
||||
%Warning-WIDTH: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
|
||||
: ... In instance t
|
||||
23 | .outy_w92 (outc_w30),
|
||||
| ^~~~~~~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTH: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits.
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHTRUNC: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits.
|
||||
: ... In instance t
|
||||
24 | .outz_w22 (outd_w73),
|
||||
| ^~~~~~~~
|
||||
%Warning-WIDTH: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits.
|
||||
: ... In instance t
|
||||
27 | .inw_w31 (ina_w1),
|
||||
| ^~~~~~~
|
||||
%Warning-WIDTH: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits.
|
||||
: ... In instance t
|
||||
28 | .inx_w11 (inb_w61)
|
||||
| ^~~~~~~
|
||||
%Error: Exiting due to
|
||||
|
@ -1,6 +1,6 @@
|
||||
%Warning-WIDTH: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256
|
||||
%Warning-WIDTHTRUNC: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256
|
||||
10 | localparam the_localparam = 8'd256;
|
||||
| ^~~~~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,7 +1,7 @@
|
||||
%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
|
||||
: ... In instance t.sub3
|
||||
%Warning-WIDTHTRUNC: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
|
||||
: ... In instance t.sub3
|
||||
18 | wire [0:0] b = a;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,7 +1,7 @@
|
||||
%Warning-WIDTH: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
|
||||
: ... In instance t
|
||||
19 | initial five = 64'h1;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,47 +1,47 @@
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
|
||||
: ... In instance t
|
||||
17 | localparam [3:0] XS = 'hx;
|
||||
| ^~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
|
||||
: ... In instance t.p4
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
|
||||
: ... In instance t.p4
|
||||
47 | wire [4:0] out = in;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
|
||||
: ... In instance t
|
||||
21 | wire [4:0] d = (1'b1 << 2) + 5'b1;
|
||||
| ^~
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
|
||||
: ... In instance t
|
||||
27 | wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
32 | wire [2:0] cnt = (one + one + one + one);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
32 | wire [2:0] cnt = (one + one + one + one);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
32 | wire [2:0] cnt = (one + one + one + one);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
|
||||
: ... In instance t
|
||||
32 | wire [2:0] cnt = (one + one + one + one);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits.
|
||||
: ... In instance t
|
||||
37 | initial for (a = 0; a > THREE; ++a) $display(a);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits.
|
||||
: ... In instance t
|
||||
38 | initial for (a = 0; a >= THREE; ++a) $display(a);
|
||||
| ^~
|
||||
%Warning-WIDTH: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits.
|
||||
: ... In instance t
|
||||
40 | initial if (THREE) $stop;
|
||||
| ^~
|
||||
%Error: Exiting due to
|
||||
|
@ -1,7 +0,0 @@
|
||||
%Warning-WIDTH: t/t_lint_width_docs_bad.v:10:29: Bit extraction of array[4:0] requires 3 bit index, not 2 bits.
|
||||
: ... In instance t
|
||||
10 | wire int rd_value = array[rd_addr];
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
@ -1,23 +1,23 @@
|
||||
%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits.
|
||||
: ... In instance t
|
||||
25 | rg = g;
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits.
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits.
|
||||
: ... In instance t
|
||||
26 | rp = P;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits.
|
||||
: ... In instance t
|
||||
27 | rw = w;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
|
||||
: ... In instance t
|
||||
28 | rc = 64'h1;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.
|
||||
: ... In instance t
|
||||
33 | ri = i;
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
7
test_regress/t/t_lint_widthexpand_docs_bad.out
Normal file
7
test_regress/t/t_lint_widthexpand_docs_bad.out
Normal file
@ -0,0 +1,7 @@
|
||||
%Warning-WIDTHEXPAND: t/t_lint_widthexpand_docs_bad.v:10:29: Bit extraction of array[4:0] requires 3 bit index, not 2 bits.
|
||||
: ... In instance t
|
||||
10 | wire int rd_value = array[rd_addr];
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
@ -18,18 +18,18 @@ lint(
|
||||
|
||||
extract(
|
||||
in => $Self->{top_filename},
|
||||
out => "../docs/gen/ex_WIDTH_1_faulty.rst",
|
||||
out => "../docs/gen/ex_WIDTHEXPAND_1_faulty.rst",
|
||||
lines => "8-10");
|
||||
|
||||
extract(
|
||||
in => $Self->{golden_filename},
|
||||
out => "../docs/gen/ex_WIDTH_1_msg.rst",
|
||||
out => "../docs/gen/ex_WIDTHEXPAND_1_msg.rst",
|
||||
lineno_adjust => -7,
|
||||
regexp => qr/Warning-WIDTH/);
|
||||
|
||||
extract(
|
||||
in => $Self->{top_filename},
|
||||
out => "../docs/gen/ex_WIDTH_1_fixed.rst",
|
||||
out => "../docs/gen/ex_WIDTHEXPAND_1_fixed.rst",
|
||||
lines => "18");
|
||||
|
||||
ok(1);
|
@ -2,12 +2,12 @@
|
||||
: ... In instance t
|
||||
12 | o = {0 {1'b1}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_math_repl_bad.v:12:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_math_repl_bad.v:12:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits.
|
||||
: ... In instance t
|
||||
12 | o = {0 {1'b1}};
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Error: t/t_math_repl_bad.v:13:12: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
|
||||
: ... In instance t
|
||||
13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}};
|
||||
|
@ -2,12 +2,12 @@
|
||||
: ... In instance t
|
||||
7 | module t #(parameter P);
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits.
|
||||
: ... In instance t
|
||||
10 | for (j=0; P; j++)
|
||||
| ^~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j'
|
||||
: ... In instance t
|
||||
10 | for (j=0; P; j++)
|
||||
|
@ -1,7 +1,7 @@
|
||||
%Warning-WIDTH: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
|
||||
: ... In instance t.test_i
|
||||
%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
|
||||
: ... In instance t.test_i
|
||||
25 | parameter logic param = 1'b0
|
||||
| ^~~~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -11,11 +11,11 @@
|
||||
20 | sel2 = mi[44 +: -1];
|
||||
| ^
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits.
|
||||
: ... In instance t
|
||||
20 | sel2 = mi[44 +: -1];
|
||||
| ^
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Error: t/t_select_bad_range4.v:21:16: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000
|
||||
: ... In instance t
|
||||
21 | sel2 = mi[44 +: 1<<29];
|
||||
@ -28,8 +28,8 @@
|
||||
: ... In instance t
|
||||
21 | sel2 = mi[44 +: 1<<29];
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000000 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000000 bits.
|
||||
: ... In instance t
|
||||
21 | sel2 = mi[44 +: 1<<29];
|
||||
| ^
|
||||
%Error: t/t_select_bad_range4.v:22:23: Expecting expression to be constant, but variable isn't const: 'nonconst'
|
||||
@ -40,16 +40,16 @@
|
||||
: ... In instance t
|
||||
22 | sel2 = mi[44 +: nonconst];
|
||||
| ^~~~~~~~
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
|
||||
: ... In instance t
|
||||
22 | sel2 = mi[44 +: nonconst];
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:23:17: Operator SUB expects 20 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:17: Operator SUB expects 20 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits.
|
||||
: ... In instance t
|
||||
23 | sel2 = mi[nonconst];
|
||||
| ^~~~~~~~
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
|
||||
: ... In instance t
|
||||
23 | sel2 = mi[nonconst];
|
||||
| ^
|
||||
%Error: t/t_select_bad_range4.v:24:17: Expecting expression to be constant, but variable isn't const: 'nonconst'
|
||||
@ -68,8 +68,8 @@
|
||||
: ... In instance t
|
||||
24 | sel2 = mi[nonconst : nonconst];
|
||||
| ^~~~~~~~
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
|
||||
: ... In instance t
|
||||
24 | sel2 = mi[nonconst : nonconst];
|
||||
| ^
|
||||
%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 20000001 bits from only 6 bit number
|
||||
@ -80,8 +80,8 @@
|
||||
: ... In instance t
|
||||
25 | sel2 = mi[1<<29 : 0];
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000001 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000001 bits.
|
||||
: ... In instance t
|
||||
25 | sel2 = mi[1<<29 : 0];
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
@ -12,8 +12,8 @@
|
||||
: ... In instance t
|
||||
16 | assign mi = unk[3:2];
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits.
|
||||
: ... In instance t
|
||||
16 | assign mi = unk[3:2];
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
@ -19,8 +19,8 @@
|
||||
: ... In instance t.i_sub3
|
||||
90 | assign outwires[12] = inwires[13];
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits.
|
||||
: ... In instance t
|
||||
41 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0);
|
||||
| ^
|
||||
%Error: t/t_split_var_1_bad.v:79:16: Illegal assignment of constant to unpacked array
|
||||
|
@ -6,10 +6,10 @@
|
||||
: ... In instance t
|
||||
12 | initial packed_data_32 = {<<$random{byte_in}};
|
||||
| ^~
|
||||
%Warning-WIDTH: t/t_stream_bad.v:12:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_bad.v:12:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
12 | initial packed_data_32 = {<<$random{byte_in}};
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,147 +1,147 @@
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:118:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:118:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
118 | packed_data_32 = {<<8{byte_in}};
|
||||
| ^
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:119:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
|
||||
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:119:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
119 | packed_data_64 = {<<16{shortint_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:120:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:120:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
120 | packed_data_128 = {<<32{int_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:121:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:121:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
121 | packed_data_128_i = {<<32{integer_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:122:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:122:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
122 | packed_data_256 = {<<64{longint_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:123:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:123:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
123 | packed_time_256 = {<<64{time_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:124:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:124:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
124 | v_packed_data_32 = {<<8{bit_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:125:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:125:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
125 | v_packed_data_64 = {<<16{logic_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:126:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:126:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
126 | v_packed_data_128 = {<<32{reg_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:128:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:128:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
128 | {<<8{byte_out}} = packed_data_32;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:129:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:129:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
129 | {<<16{shortint_out}} = packed_data_64;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:130:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:130:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
130 | {<<32{int_out}} = packed_data_128;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:131:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:131:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits.
|
||||
: ... In instance t
|
||||
131 | {<<32{integer_out}} = packed_data_128_i;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:132:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:132:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
132 | {<<64{longint_out}} = packed_data_256;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:133:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:133:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
133 | {<<64{time_out}} = packed_time_256;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:134:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:134:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
134 | {<<8{bit_out}} = v_packed_data_32;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:135:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:135:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
135 | {<<16{logic_out}} = v_packed_data_64;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:136:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:136:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
136 | {<<32{reg_out}} = v_packed_data_128;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:150:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:150:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
150 | packed_data_32 = {<<byte{byte_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:151:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:151:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
151 | packed_data_64 = {<<shortint{shortint_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:152:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:152:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
152 | packed_data_128 = {<<int{int_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:153:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:153:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
153 | packed_data_128_i = {<<integer{integer_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:154:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:154:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
154 | packed_data_256 = {<<longint{longint_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:155:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:155:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
|
||||
: ... In instance t
|
||||
155 | packed_time_256 = {<<time{time_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:156:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:156:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
|
||||
: ... In instance t
|
||||
156 | v_packed_data_32 = {<<test_byte{bit_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:157:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:157:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
|
||||
: ... In instance t
|
||||
157 | v_packed_data_64 = {<<test_short{logic_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:158:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:158:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
|
||||
: ... In instance t
|
||||
158 | v_packed_data_128 = {<<test_word{reg_in}};
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:160:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:160:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
160 | {<<byte{byte_out}} = packed_data_32;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:161:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:161:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
161 | {<<shortint{shortint_out}} = packed_data_64;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:162:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:162:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
162 | {<<int{int_out}} = packed_data_128;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:163:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:163:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits.
|
||||
: ... In instance t
|
||||
163 | {<<integer{integer_out}} = packed_data_128_i;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:164:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:164:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
164 | {<<longint{longint_out}} = packed_data_256;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:165:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:165:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits.
|
||||
: ... In instance t
|
||||
165 | {<<time{time_out}} = packed_time_256;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:166:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:166:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits.
|
||||
: ... In instance t
|
||||
166 | {<<test_byte{bit_out}} = v_packed_data_32;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:167:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:167:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits.
|
||||
: ... In instance t
|
||||
167 | {<<test_short{logic_out}} = v_packed_data_64;
|
||||
| ^
|
||||
%Warning-WIDTH: t/t_stream_integer_type.v:168:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:168:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits.
|
||||
: ... In instance t
|
||||
168 | {<<test_word{reg_out}} = v_packed_data_128;
|
||||
| ^
|
||||
%Error: t/t_stream_integer_type.v:128:11: SEL is not an unpacked array, but is in an unpacked array context
|
||||
|
@ -3,9 +3,9 @@
|
||||
9 | if ($) $stop;
|
||||
| ^
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Warning-WIDTH: t/t_unbounded_bad.v:9:7: Logical operator IF expects 1 bit on the If, but If's UNBOUNDED generates 32 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_unbounded_bad.v:9:7: Logical operator IF expects 1 bit on the If, but If's UNBOUNDED generates 32 bits.
|
||||
: ... In instance t
|
||||
9 | if ($) $stop;
|
||||
| ^~
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -1,7 +1,7 @@
|
||||
%Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits.
|
||||
: ... In instance t
|
||||
%Warning-WIDTHTRUNC: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits.
|
||||
: ... In instance t
|
||||
21 | reg width_warn3_var_line20 = 2'b11;
|
||||
| ^~~~~
|
||||
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
||||
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||||
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
|
||||
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
@ -7,7 +7,7 @@
|
||||
// 2. Keep the waiver permanently if you are sure this is okay
|
||||
// 3. Keep the waiver temporarily to suppress the output
|
||||
|
||||
// lint_off -rule WIDTH -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits."
|
||||
// lint_off -rule WIDTHTRUNC -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits."
|
||||
|
||||
// lint_off -rule UNUSEDSIGNAL -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'"
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user