forked from github/verilator
131 lines
3.0 KiB
Systemverilog
131 lines
3.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Alex Solomatnikov.
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// SPDX-License-Identifier: CC0-1.0
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interface hex2ram_if
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(
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input bit trigger
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);
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string instance_path = $sformatf("%m");
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string testfile = "";
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bit has_testfile = |($value$plusargs("testfile=%s", testfile));
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bit armed = 1'b1;
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bit armed_trigger;
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initial begin
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$display("successfully bound hex2ram_if to %s", instance_path);
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armed = has_testfile && 1'b1;
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end
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assign armed_trigger = armed && trigger;
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always @(posedge armed_trigger) begin
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$display("%m(%0t): saw deassertion of reset", $time);
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end
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endinterface : hex2ram_if
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module t
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(
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clk
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);
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input clk /*verilator clocker*/;
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bit reset;
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wire success;
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SimpleTestHarness testHarness
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(
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.clk(clk),
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.reset(reset),
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.io_success(success)
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);
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integer cyc = 0;
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always @ (posedge clk) begin
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cyc = cyc + 1;
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if (cyc<10) begin
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reset <= '0;
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end
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else if (cyc<20) begin
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reset <= '1;
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end
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else if (cyc<30) begin
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reset <= '0;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset));
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module testharness_ext
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(
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input W0_clk,
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input [24:0] W0_addr,
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input W0_en,
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input [127:0] W0_data,
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input [0:0] W0_mask,
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input R0_clk,
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input [24:0] R0_addr,
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input R0_en,
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output [127:0] R0_data
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);
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reg [24:0] reg_R0_addr;
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wire [127:0] R0_rdata_mask;
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reg [127:0] ram [33554431:0];
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wire [127:0] W0_wdata_mask;
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always @(posedge R0_clk)
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if (R0_en) reg_R0_addr <= R0_addr;
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always @(posedge W0_clk)
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if (W0_en) begin
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if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask;
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end
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assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;;
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assign R0_rdata_mask = 0;
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assign W0_wdata_mask = 0;
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endmodule
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module SimpleTestHarness
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(
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input clk,
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input reset,
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output io_success);
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wire [24:0] testharness_ext_R0_addr;
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wire testharness_ext_R0_en;
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wire testharness_ext_R0_clk;
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wire [127:0] testharness_ext_R0_data;
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wire [24:0] testharness_ext_W0_addr;
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wire testharness_ext_W0_en;
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wire testharness_ext_W0_clk;
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wire [127:0] testharness_ext_W0_data;
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wire [0:0] testharness_ext_W0_mask;
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testharness_ext testharness_ext
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(
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.R0_addr(testharness_ext_R0_addr),
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.R0_en(testharness_ext_R0_en),
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.R0_clk(testharness_ext_R0_clk),
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.R0_data(testharness_ext_R0_data),
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.W0_addr(testharness_ext_W0_addr),
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.W0_en(testharness_ext_W0_en),
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.W0_clk(testharness_ext_W0_clk),
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.W0_data(testharness_ext_W0_data),
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.W0_mask(testharness_ext_W0_mask)
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);
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endmodule
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