forked from github/verilator
62 lines
1.2 KiB
Systemverilog
62 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Drew Ranck.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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always @ (posedge clk) begin : main
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cyc <= cyc + 1;
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if (cyc > 100) begin
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$write("*-* All Finished *-*\n");
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$finish();
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end
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end
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logic [3:0] count_d;
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logic [3:0] count_q = '0;
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logic [3:0] want_count_d;
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logic [3:0] want_count_q = '0;
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always_ff @(posedge clk) begin : flops
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count_q <= count_d;
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want_count_q <= want_count_d;
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end
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always @(posedge clk) begin : simple_check
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if (cyc > 0) begin
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if (count_q !== want_count_q) begin
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$error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)",
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cyc, count_q, want_count_q);
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$stop; // don't finish to fail the test.
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end
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end
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end
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always_comb begin : update_golden_counts
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want_count_d = want_count_q;
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want_count_d += 1'b1;
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end
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// make sure an implicit void cast on n++ works as expected.
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always_comb begin : update_counts
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count_d = count_q;
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count_d++;
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end
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endmodule
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