Commentary

This commit is contained in:
Wilson Snyder 2023-02-28 18:38:52 -05:00
parent 06661ab676
commit c6a569df49

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@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Drew Ranck.
// SPDX-License-Identifier: CC0-1.0
module t
(/*AUTOARG*/
// Inputs