forked from github/verilator
f8c0169e82
Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code.
10 lines
264 B
Plaintext
10 lines
264 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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forceable -module "*" -var "var_*"
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