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Implement 'forceable' attribute

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Using the 'forceable' directive in a configuration file, or the /*
verilator forceable */ metacomment on a variable declaration will
generate additional public signals that allow the specified signals to
be forced/released from the C++ code.
This commit is contained in:
Geza Lore 2021-12-19 19:45:06 +00:00
parent 539c9d4c63
commit f8c0169e82
27 changed files with 1196 additions and 6 deletions
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1
Changes
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@ -23,6 +23,7 @@ Verilator 4.217 devel
* Support class static members (#2233).
* Support force/release (#2431) (#2593). [Shunyao CAD]
* Add 'forceable' attribute to allow forcing from C++. (#3272). [Geza Lore, Shunyao CAD]
* Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim]
* Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman]
* Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD]

8
docs/guide/exe_verilator.rst
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@ -1529,6 +1529,14 @@ The grammar of configuration commands is as follows:
Same as :option:`/*verilator&32;coverage_block_off*/` metacomment.
.. option:: forceable -module "<modulename>" -var "<signame>"
Generate public `<signame>__VforceEn` and `<signame>__VforceVal` signals
that can be used to force/release a signal from C++ code. The force control
signals are created as :option:`public_flat` signals.
Same as :option:`/*verilator&32;forceable*/` metacomment.
.. option:: full_case -file "<filename>" -lines <lineno>
.. option:: parallel_case -file "<filename>" -lines <lineno>

14
docs/guide/extensions.rst
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@ -209,6 +209,20 @@ or "`ifdef`"'s may break other tools.
(if appropriate :vlopt:`--coverage` flags are passed) after being
disabled earlier with :option:`/*verilator&32;coverage_off*/`.
.. option:: /*verilator&32;forceable*/
Specifies that the signal (net or variable) should be made forceable from
C++ code by generating public `<signame>__VforceEn` and
`<signame>__VforceVal` signals The force control signals are created as
:option:`public_flat` signals.
To force a marked signal from C++, set the corresponding `__VforceVal`
variable to the desired value, and the `__VforceEn` signal to the bitmask
indicating which bits of the signal to force. To force all bits of the
target signal, set `__VforceEn` to all ones. To release the signal (or part
thereof), set appropriate bits of the `__VforceEn` signal to zero.
Same as :option:`forceable` in configuration files.
.. _verilator_hier_block:

3
src/V3Ast.h
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@ -372,6 +372,7 @@ public:
//
VAR_BASE, // V3LinkResolve creates for AstPreSel, V3LinkParam removes
VAR_CLOCK_ENABLE, // V3LinkParse moves to AstVar::attrClockEn
VAR_FORCEABLE, // V3LinkParse moves to AstVar::isForceable
VAR_PUBLIC, // V3LinkParse moves to AstVar::sigPublic
VAR_PUBLIC_FLAT, // V3LinkParse moves to AstVar::sigPublic
VAR_PUBLIC_FLAT_RD, // V3LinkParse moves to AstVar::sigPublic
@ -396,7 +397,7 @@ public:
"ENUM_NEXT", "ENUM_PREV", "ENUM_NAME", "ENUM_VALID",
"MEMBER_BASE",
"TYPENAME",
"VAR_BASE", "VAR_CLOCK_ENABLE", "VAR_PUBLIC",
"VAR_BASE", "VAR_CLOCK_ENABLE", "VAR_FORCEABLE", "VAR_PUBLIC",
"VAR_PUBLIC_FLAT", "VAR_PUBLIC_FLAT_RD", "VAR_PUBLIC_FLAT_RW",
"VAR_ISOLATE_ASSIGNMENTS", "VAR_SC_BV", "VAR_SFORMAT", "VAR_CLOCKER",
"VAR_NO_CLOCKER", "VAR_SPLIT_VAR"

4
src/V3AstNodes.h
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@ -2000,6 +2000,7 @@ private:
bool m_overridenParam : 1; // Overridden parameter by #(...) or defparam
bool m_trace : 1; // Trace this variable
bool m_isLatched : 1; // Not assigned in all control paths of combo always
bool m_isForceable : 1; // May be forced/released externally from user C code
void init() {
m_ansi = false;
@ -2039,6 +2040,7 @@ private:
m_overridenParam = false;
m_trace = false;
m_isLatched = false;
m_isForceable = false;
m_attrClocker = VVarAttrClocker::CLOCKER_UNKNOWN;
}
@ -2200,6 +2202,8 @@ public:
bool overriddenParam() const { return m_overridenParam; }
void trace(bool flag) { m_trace = flag; }
void isLatched(bool flag) { m_isLatched = flag; }
bool isForceable() const { return m_isForceable; }
void setForceable() { m_isForceable = true; }
// METHODS
virtual void name(const string& name) override { m_name = name; }
virtual void tag(const string& text) override { m_tag = text; }

24
src/V3Config.cpp
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@ -87,6 +87,9 @@ class V3ConfigVarAttr final {
public:
VAttrType m_type; // Type of attribute
AstSenTree* m_sentreep; // Sensitivity tree for public_flat_rw
explicit V3ConfigVarAttr(VAttrType type)
: m_type{type}
, m_sentreep{nullptr} {}
V3ConfigVarAttr(VAttrType type, AstSenTree* sentreep)
: m_type{type}
, m_sentreep{sentreep} {}
@ -455,14 +458,25 @@ void V3Config::addVarAttr(FileLine* fl, const string& module, const string& ftas
V3ConfigResolver::s().modules().at(module).ftasks().at(ftask).setPublic(true);
}
} else {
fl->v3error("missing -signal");
fl->v3error("missing -var");
}
} else {
V3ConfigModule& mod = V3ConfigResolver::s().modules().at(module);
if (ftask.empty()) {
mod.vars().at(var).push_back(V3ConfigVarAttr(attr, sensep));
if (attr == VAttrType::VAR_FORCEABLE) {
if (module.empty()) {
fl->v3error("missing -module");
} else if (!ftask.empty()) {
fl->v3error("Signals inside functions/tasks cannot be marked forceable");
} else {
V3ConfigResolver::s().modules().at(module).vars().at(var).push_back(
V3ConfigVarAttr(attr));
}
} else {
mod.ftasks().at(ftask).vars().at(var).push_back(V3ConfigVarAttr(attr, sensep));
V3ConfigModule& mod = V3ConfigResolver::s().modules().at(module);
if (ftask.empty()) {
mod.vars().at(var).push_back(V3ConfigVarAttr(attr, sensep));
} else {
mod.ftasks().at(ftask).vars().at(var).push_back(V3ConfigVarAttr(attr, sensep));
}
}
}
}

9
src/V3Force.cpp
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@ -256,6 +256,15 @@ class ForceConvertVisitor final : public VNVisitor {
relinker.relink(resetEnp);
}
void visit(AstVarScope* nodep) override {
// If this signal is marked externally forceable, create the public force signals
if (nodep->varp()->isForceable()) {
const ForceComponentsVarScope& fc = getForceComponents(nodep);
fc.m_enVscp->varp()->sigPublic(true);
fc.m_valVscp->varp()->sigPublic(true);
}
}
// CONSTRUCTOR
explicit ForceConvertVisitor(AstNetlist* nodep) {
// Transform all force and release statements

5
src/V3LinkParse.cpp
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@ -307,6 +307,11 @@ private:
UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
m_varp->attrClockEn(true);
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
} else if (nodep->attrType() == VAttrType::VAR_FORCEABLE) {
UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
m_varp->setForceable();
v3Global.setHasForceableSignals();
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
} else if (nodep->attrType() == VAttrType::VAR_PUBLIC) {
UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
m_varp->sigUserRWPublic(true);

2
src/verilog.l
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@ -112,6 +112,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"coverage_block_off" { FL; return yVLT_COVERAGE_BLOCK_OFF; }
"coverage_off" { FL; return yVLT_COVERAGE_OFF; }
"coverage_on" { FL; return yVLT_COVERAGE_ON; }
"forceable" { FL; return yVLT_FORCEABLE; }
"full_case" { FL; return yVLT_FULL_CASE; }
"hier_block" { FL; return yVLT_HIER_BLOCK; }
"inline" { FL; return yVLT_INLINE; }
@ -722,6 +723,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
"/*verilator coverage_off*/" { FL_FWD; PARSEP->lexFileline()->coverageOn(false); FL_BRK; }
"/*verilator coverage_on*/" { FL_FWD; PARSEP->lexFileline()->coverageOn(true); FL_BRK; }
"/*verilator forceable*/" { FL; return yVL_FORCEABLE; }
"/*verilator full_case*/" { FL; return yVL_FULL_CASE; }
"/*verilator hier_block*/" { FL; return yVL_HIER_BLOCK; }
"/*verilator inline_module*/" { FL; return yVL_INLINE_MODULE; }

4
src/verilog.y
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@ -340,6 +340,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yVLT_COVERAGE_BLOCK_OFF "coverage_block_off"
%token<fl> yVLT_COVERAGE_OFF "coverage_off"
%token<fl> yVLT_COVERAGE_ON "coverage_on"
%token<fl> yVLT_FORCEABLE "forceable"
%token<fl> yVLT_FULL_CASE "full_case"
%token<fl> yVLT_HIER_BLOCK "hier_block"
%token<fl> yVLT_INLINE "inline"
@ -811,6 +812,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yVL_CLOCKER "/*verilator clocker*/"
%token<fl> yVL_CLOCK_ENABLE "/*verilator clock_enable*/"
%token<fl> yVL_COVERAGE_BLOCK_OFF "/*verilator coverage_block_off*/"
%token<fl> yVL_FORCEABLE "/*verilator forceable*/"
%token<fl> yVL_FULL_CASE "/*verilator full_case*/"
%token<fl> yVL_HIER_BLOCK "/*verilator hier_block*/"
%token<fl> yVL_INLINE_MODULE "/*verilator inline_module*/"
@ -2649,6 +2651,7 @@ sigAttr<nodep>:
yVL_CLOCKER { $$ = new AstAttrOf($1,VAttrType::VAR_CLOCKER); }
| yVL_NO_CLOCKER { $$ = new AstAttrOf($1,VAttrType::VAR_NO_CLOCKER); }
| yVL_CLOCK_ENABLE { $$ = new AstAttrOf($1,VAttrType::VAR_CLOCK_ENABLE); }
| yVL_FORCEABLE { $$ = new AstAttrOf($1,VAttrType::VAR_FORCEABLE); }
| yVL_PUBLIC { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC); v3Global.dpi(true); }
| yVL_PUBLIC_FLAT { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT); v3Global.dpi(true); }
| yVL_PUBLIC_FLAT_RD { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RD); v3Global.dpi(true); }
@ -6481,6 +6484,7 @@ vltVarAttrFront<attrtypeen>:
| yVLT_CLOCKER { $$ = VAttrType::VAR_CLOCKER; }
| yVLT_ISOLATE_ASSIGNMENTS { $$ = VAttrType::VAR_ISOLATE_ASSIGNMENTS; }
| yVLT_NO_CLOCKER { $$ = VAttrType::VAR_NO_CLOCKER; }
| yVLT_FORCEABLE { $$ = VAttrType::VAR_FORCEABLE; }
| yVLT_PUBLIC { $$ = VAttrType::VAR_PUBLIC; v3Global.dpi(true); }
| yVLT_PUBLIC_FLAT { $$ = VAttrType::VAR_PUBLIC_FLAT; v3Global.dpi(true); }
| yVLT_PUBLIC_FLAT_RD { $$ = VAttrType::VAR_PUBLIC_FLAT_RD; v3Global.dpi(true); }

1
test_regress/Makefile_obj
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@ -34,6 +34,7 @@ CPPFLAGS += -DVL_DEBUG=1
CPPFLAGS += -DTEST_OBJ_DIR=$(TEST_OBJ_DIR)
CPPFLAGS += -DVM_PREFIX=$(VM_PREFIX)
CPPFLAGS += -DVM_PREFIX_INCLUDE="<$(VM_PREFIX).h>"
CPPFLAGS += -DVM_PREFIX_ROOT_INCLUDE="<$(VM_PREFIX)___024root.h>"
CPPFLAGS += $(CPPFLAGS_DRIVER)
CPPFLAGS += $(CPPFLAGS_DRIVER2)
CPPFLAGS += $(CPPFLAGS_ADD)

118
test_regress/t/t_forceable_net.cpp Normal file
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@ -0,0 +1,118 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
#include <memory>
#include "verilatedos.h"
#include "verilated.h"
#if VM_TRACE
#include "verilated_vcd_c.h"
#endif
#include VM_PREFIX_INCLUDE
#include VM_PREFIX_ROOT_INCLUDE
int main(int argc, char** argv) {
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->commandArgs(argc, argv);
contextp->debug(0);
srand48(5);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{"top"}};
topp->clk = false;
topp->rst = true;
topp->eval();
#if VM_TRACE
contextp->traceEverOn(true);
std::unique_ptr<VerilatedVcdC> tfp{new VerilatedVcdC};
topp->trace(tfp.get(), 99);
tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
tfp->dump(contextp->time());
#endif
contextp->timeInc(5);
topp->clk = true;
topp->eval();
topp->rst = false;
topp->eval();
#if VM_TRACE
tfp->dump(contextp->time());
#endif
contextp->timeInc(5);
while (contextp->time() < 1000 && !contextp->gotFinish()) {
topp->clk = !topp->clk;
topp->eval();
if (topp->clk) {
bool needsSecondEval = false;
if (topp->cyc == 3) {
topp->rootp->t__DOT__net_1__VforceEn = 1;
topp->rootp->t__DOT__net_1__VforceVal = 0;
needsSecondEval = true;
}
if (topp->cyc == 5) {
topp->rootp->t__DOT__net_1__VforceVal = 1;
needsSecondEval = true;
}
if (topp->cyc == 8) {
topp->rootp->t__DOT__net_1__VforceEn = 0;
needsSecondEval = true;
}
if (topp->cyc == 4) {
topp->rootp->t__DOT__net_8__VforceEn = 0xff;
topp->rootp->t__DOT__net_8__VforceVal = 0x5f;
needsSecondEval = true;
}
if (topp->cyc == 6) {
topp->rootp->t__DOT__net_8__VforceVal = 0xf5;
needsSecondEval = true;
}
if (topp->cyc == 9) {
topp->rootp->t__DOT__net_8__VforceEn = 0;
needsSecondEval = true;
}
if (topp->cyc == 10) {
topp->rootp->t__DOT__net_1__VforceEn = 1;
topp->rootp->t__DOT__net_8__VforceEn = 0xff;
topp->rootp->t__DOT__net_1__VforceVal = 1;
topp->rootp->t__DOT__net_8__VforceVal = 0x5a;
needsSecondEval = true;
}
if (topp->cyc == 12) {
topp->rootp->t__DOT__net_1__VforceVal = 0;
topp->rootp->t__DOT__net_8__VforceVal = 0xa5;
needsSecondEval = true;
}
if (topp->cyc == 14) {
topp->rootp->t__DOT__net_1__VforceEn = 0;
topp->rootp->t__DOT__net_8__VforceEn = 0;
needsSecondEval = true;
}
if (needsSecondEval) topp->eval();
}
#if VM_TRACE
tfp->dump(contextp->time());
#endif
contextp->timeInc(5);
}
if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
}
topp->final();
#if VM_TRACE
tfp->close();
#endif
return 0;
}

80
test_regress/t/t_forceable_net.v Normal file
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@ -0,0 +1,80 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t (
input wire clk,
input wire rst,
output reg [31:0] cyc
);
always @(posedge clk) begin
if (rst) begin
cyc <= 0;
end else begin
cyc <= cyc +1;
end
end
`ifdef CMT
wire net_1 /* verilator forceable */;
wire [7:0] net_8 /* verilator forceable */;
`else
wire net_1;
wire [7:0] net_8;
`endif
assign net_1 = ~cyc[0];
assign net_8 = ~cyc[1 +: 8];
always @ (posedge clk) begin
$display("%d: %x %x", cyc, net_8, net_1);
if (!rst) begin
case (cyc)
3: begin
`checkh (net_1, 0);
`checkh (net_8, ~cyc[1 +: 8]);
end
4: begin
`checkh (net_1, 0);
`checkh (net_8, 8'h5f);
end
5: begin
`checkh (net_1, 1);
`checkh (net_8, 8'h5f);
end
6, 7: begin
`checkh (net_1, 1);
`checkh (net_8, 8'hf5);
end
8: begin
`checkh (net_1, ~cyc[0]);
`checkh (net_8, 8'hf5);
end
10, 11: begin
`checkh (net_1, 1);
`checkh (net_8, 8'h5a);
end
12, 13: begin
`checkh (net_1, 0);
`checkh (net_8, 8'ha5);
end
default: begin
`checkh ({net_8, net_1}, ~cyc[0 +: 9]);
end
endcase
end
if (cyc == 30) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

9
test_regress/t/t_forceable_net.vlt Normal file
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@ -0,0 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`verilator_config
forceable -module "*" -var "net_*"

30
test_regress/t/t_forceable_net_cmt.pl Executable file
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@ -0,0 +1,30 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_net.v");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'-DCMT=1',
'--exe',
"$Self->{t_dir}/t_forceable_net.cpp"
],
);
execute(
check_finished => 1,
);
ok(1);
1;

34
test_regress/t/t_forceable_net_cmt_trace.pl Executable file
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@ -0,0 +1,34 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_net.v");
golden_filename("t/t_forceable_net_trace.vcd");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'-DCMT=1',
'--exe',
'--trace',
"$Self->{t_dir}/t_forceable_net.cpp"
],
);
execute(
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
ok(1);
1;

223
test_regress/t/t_forceable_net_trace.vcd Normal file
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@ -0,0 +1,223 @@
$version Generated by VerilatedVcd $end
$date Sun Dec 19 19:39:17 2021 $end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$var wire 32 % cyc [31:0] $end
$var wire 1 $ rst $end
$scope module t $end
$var wire 1 # clk $end
$var wire 32 % cyc [31:0] $end
$var wire 1 & net_1 $end
$var wire 8 ' net_8 [7:0] $end
$var wire 1 $ rst $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
1$
b00000000000000000000000000000000 %
1&
b11111111 '
#5
1#
0$
#10
0#
#15
1#
b00000000000000000000000000000001 %
0&
#20
0#
#25
1#
b00000000000000000000000000000010 %
1&
b11111110 '
#30
0#
#35
1#
b00000000000000000000000000000011 %
0&
#40
0#
#45
1#
b00000000000000000000000000000100 %
b01011111 '
#50
0#
#55
1#
b00000000000000000000000000000101 %
1&
#60
0#
#65
1#
b00000000000000000000000000000110 %
b11110101 '
#70
0#
#75
1#
b00000000000000000000000000000111 %
#80
0#
#85
1#
b00000000000000000000000000001000 %
#90
0#
#95
1#
b00000000000000000000000000001001 %
0&
b11111011 '
#100
0#
#105
1#
b00000000000000000000000000001010 %
1&
b01011010 '
#110
0#
#115
1#
b00000000000000000000000000001011 %
#120
0#
#125
1#
b00000000000000000000000000001100 %
0&
b10100101 '
#130
0#
#135
1#
b00000000000000000000000000001101 %
#140
0#
#145
1#
b00000000000000000000000000001110 %
1&
b11111000 '
#150
0#
#155
1#
b00000000000000000000000000001111 %
0&
#160
0#
#165
1#
b00000000000000000000000000010000 %
1&
b11110111 '
#170
0#
#175
1#
b00000000000000000000000000010001 %
0&
#180
0#
#185
1#
b00000000000000000000000000010010 %
1&
b11110110 '
#190
0#
#195
1#
b00000000000000000000000000010011 %
0&
#200
0#
#205
1#
b00000000000000000000000000010100 %
1&
b11110101 '
#210
0#
#215
1#
b00000000000000000000000000010101 %
0&
#220
0#
#225
1#
b00000000000000000000000000010110 %
1&
b11110100 '
#230
0#
#235
1#
b00000000000000000000000000010111 %
0&
#240
0#
#245
1#
b00000000000000000000000000011000 %
1&
b11110011 '
#250
0#
#255
1#
b00000000000000000000000000011001 %
0&
#260
0#
#265
1#
b00000000000000000000000000011010 %
1&
b11110010 '
#270
0#
#275
1#
b00000000000000000000000000011011 %
0&
#280
0#
#285
1#
b00000000000000000000000000011100 %
1&
b11110001 '
#290
0#
#295
1#
b00000000000000000000000000011101 %
0&
#300
0#
#305
1#
b00000000000000000000000000011110 %
1&
b11110000 '
#310
0#
#315
1#
b00000000000000000000000000011111 %
0&

30
test_regress/t/t_forceable_net_vlt.pl Executable file
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@ -0,0 +1,30 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_net.v");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'--exe',
"$Self->{t_dir}/t_forceable_net.cpp",
"$Self->{t_dir}/t_forceable_net.vlt"
],
);
execute(
check_finished => 1,
);
ok(1);
1;

34
test_regress/t/t_forceable_net_vlt_trace.pl Executable file
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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_net.v");
golden_filename("t/t_forceable_net_trace.vcd");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'--exe',
'--trace',
"$Self->{t_dir}/t_forceable_net.cpp",
"$Self->{t_dir}/t_forceable_net.vlt"
],
);
execute(
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
ok(1);
1;

118
test_regress/t/t_forceable_var.cpp Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
#include <memory>
#include "verilatedos.h"
#include "verilated.h"
#if VM_TRACE
#include "verilated_vcd_c.h"
#endif
#include VM_PREFIX_INCLUDE
#include VM_PREFIX_ROOT_INCLUDE
int main(int argc, char** argv) {
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->commandArgs(argc, argv);
contextp->debug(0);
srand48(5);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{"top"}};
topp->clk = false;
topp->rst = true;
topp->eval();
#if VM_TRACE
contextp->traceEverOn(true);
std::unique_ptr<VerilatedVcdC> tfp{new VerilatedVcdC};
topp->trace(tfp.get(), 99);
tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
tfp->dump(contextp->time());
#endif
contextp->timeInc(5);
topp->clk = true;
topp->eval();
topp->rst = false;
topp->eval();
#if VM_TRACE
tfp->dump(contextp->time());
#endif
contextp->timeInc(5);
while (contextp->time() < 1000 && !contextp->gotFinish()) {
topp->clk = !topp->clk;
topp->eval();
if (topp->clk) {
bool needsSecondEval = false;
if (topp->cyc == 13) {
topp->rootp->t__DOT__var_1__VforceEn = 1;
topp->rootp->t__DOT__var_1__VforceVal = 1;
needsSecondEval = true;
}
if (topp->cyc == 15) {
topp->rootp->t__DOT__var_1__VforceVal = 0;
needsSecondEval = true;
}
if (topp->cyc == 18) {
topp->rootp->t__DOT__var_1__VforceEn = 0;
needsSecondEval = true;
}
if (topp->cyc == 14) {
topp->rootp->t__DOT__var_8__VforceEn = 0xff;
topp->rootp->t__DOT__var_8__VforceVal = 0xf5;
needsSecondEval = true;
}
if (topp->cyc == 16) {
topp->rootp->t__DOT__var_8__VforceVal = 0x5f;
needsSecondEval = true;
}
if (topp->cyc == 19) {
topp->rootp->t__DOT__var_8__VforceEn = 0;
needsSecondEval = true;
}
if (topp->cyc == 20) {
topp->rootp->t__DOT__var_1__VforceEn = 1;
topp->rootp->t__DOT__var_8__VforceEn = 0xff;
topp->rootp->t__DOT__var_1__VforceVal = 1;
topp->rootp->t__DOT__var_8__VforceVal = 0x5a;
needsSecondEval = true;
}
if (topp->cyc == 22) {
topp->rootp->t__DOT__var_1__VforceVal = 0;
topp->rootp->t__DOT__var_8__VforceVal = 0xa5;
needsSecondEval = true;
}
if (topp->cyc == 24) {
topp->rootp->t__DOT__var_1__VforceEn = 0;
topp->rootp->t__DOT__var_8__VforceEn = 0;
needsSecondEval = true;
}
if (needsSecondEval) topp->eval();
}
#if VM_TRACE
tfp->dump(contextp->time());
#endif
contextp->timeInc(5);
}
if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
}
topp->final();
#if VM_TRACE
tfp->close();
#endif
return 0;
}

91
test_regress/t/t_forceable_var.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t (
input wire clk,
input wire rst,
output reg [31:0] cyc
);
always @(posedge clk) begin
if (rst) begin
cyc <= 0;
end else begin
cyc <= cyc +1;
end
end
`ifdef CMT
reg var_1 /* verilator forceable */;
reg [7:0] var_8 /* verilator forceable */;
`else
reg var_1;
reg [7:0] var_8;
`endif
always @(posedge clk) begin
if (rst) begin
var_1 <= 0;
var_8 <= 0;
end else begin
var_1 <= cyc[0];
var_8 <= cyc[1 +: 8];
end
end
always @ (posedge clk) begin
$display("%d: %x %x", cyc, var_8, var_1);
if (!rst) begin
case (cyc)
0: begin // Reset values
`checkh (var_1, 0);
`checkh (var_8, 0);
end
13: begin
`checkh (var_1, 1);
`checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1);
end
14: begin
`checkh (var_1, 1);
`checkh (var_8, 8'hf5);
end
15: begin
`checkh (var_1, 0);
`checkh (var_8, 8'hf5);
end
16, 17: begin
`checkh (var_1, 0);
`checkh (var_8, 8'h5f);
end
18: begin
`checkh (var_1, ~cyc[0]);
`checkh (var_8, 8'h5f);
end
20, 21: begin
`checkh (var_1, 1);
`checkh (var_8, 8'h5a);
end
22, 23: begin
`checkh (var_1, 0);
`checkh (var_8, 8'ha5);
end
default: begin
`checkh ({var_8, var_1}, cyc[0 +: 9] - 1);
end
endcase
end
if (cyc == 30) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

9
test_regress/t/t_forceable_var.vlt Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`verilator_config
forceable -module "*" -var "var_*"

30
test_regress/t/t_forceable_var_cmt.pl Executable file
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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_var.v");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'-DCMT=1',
'--exe',
"$Self->{t_dir}/t_forceable_var.cpp"
],
);
execute(
check_finished => 1,
);
ok(1);
1;

34
test_regress/t/t_forceable_var_cmt_trace.pl Executable file
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@ -0,0 +1,34 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_var.v");
golden_filename("t/t_forceable_var_trace.vcd");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'-DCMT=1',
'--exe',
'--trace',
"$Self->{t_dir}/t_forceable_var.cpp"
],
);
execute(
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
ok(1);
1;

223
test_regress/t/t_forceable_var_trace.vcd Normal file
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@ -0,0 +1,223 @@
$version Generated by VerilatedVcd $end
$date Sun Dec 19 19:26:33 2021 $end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$var wire 32 % cyc [31:0] $end
$var wire 1 $ rst $end
$scope module t $end
$var wire 1 # clk $end
$var wire 32 % cyc [31:0] $end
$var wire 1 $ rst $end
$var wire 1 & var_1 $end
$var wire 8 ' var_8 [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
1$
b00000000000000000000000000000000 %
0&
b00000000 '
#5
1#
0$
#10
0#
#15
1#
b00000000000000000000000000000001 %
#20
0#
#25
1#
b00000000000000000000000000000010 %
1&
#30
0#
#35
1#
b00000000000000000000000000000011 %
0&
b00000001 '
#40
0#
#45
1#
b00000000000000000000000000000100 %
1&
#50
0#
#55
1#
b00000000000000000000000000000101 %
0&
b00000010 '
#60
0#
#65
1#
b00000000000000000000000000000110 %
1&
#70
0#
#75
1#
b00000000000000000000000000000111 %
0&
b00000011 '
#80
0#
#85
1#
b00000000000000000000000000001000 %
1&
#90
0#
#95
1#
b00000000000000000000000000001001 %
0&
b00000100 '
#100
0#
#105
1#
b00000000000000000000000000001010 %
1&
#110
0#
#115
1#
b00000000000000000000000000001011 %
0&
b00000101 '
#120
0#
#125
1#
b00000000000000000000000000001100 %
1&
#130
0#
#135
1#
b00000000000000000000000000001101 %
b00000110 '
#140
0#
#145
1#
b00000000000000000000000000001110 %
b11110101 '
#150
0#
#155
1#
b00000000000000000000000000001111 %
0&
#160
0#
#165
1#
b00000000000000000000000000010000 %
b01011111 '
#170
0#
#175
1#
b00000000000000000000000000010001 %
#180
0#
#185
1#
b00000000000000000000000000010010 %
1&
#190
0#
#195
1#
b00000000000000000000000000010011 %
0&
b00001001 '
#200
0#
#205
1#
b00000000000000000000000000010100 %
1&
b01011010 '
#210
0#
#215
1#
b00000000000000000000000000010101 %
#220
0#
#225
1#
b00000000000000000000000000010110 %
0&
b10100101 '
#230
0#
#235
1#
b00000000000000000000000000010111 %
#240
0#
#245
1#
b00000000000000000000000000011000 %
1&
b00001011 '
#250
0#
#255
1#
b00000000000000000000000000011001 %
0&
b00001100 '
#260
0#
#265
1#
b00000000000000000000000000011010 %
1&
#270
0#
#275
1#
b00000000000000000000000000011011 %
0&
b00001101 '
#280
0#
#285
1#
b00000000000000000000000000011100 %
1&
#290
0#
#295
1#
b00000000000000000000000000011101 %
0&
b00001110 '
#300
0#
#305
1#
b00000000000000000000000000011110 %
1&
#310
0#
#315
1#
b00000000000000000000000000011111 %
0&
b00001111 '

30
test_regress/t/t_forceable_var_vlt.pl Executable file
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@ -0,0 +1,30 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_var.v");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'--exe',
"$Self->{t_dir}/t_forceable_var.cpp",
"$Self->{t_dir}/t_forceable_var.vlt"
],
);
execute(
check_finished => 1,
);
ok(1);
1;

34
test_regress/t/t_forceable_var_vlt_trace.pl Executable file
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@ -0,0 +1,34 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_forceable_var.v");
golden_filename("t/t_forceable_var_trace.vcd");
compile(
make_top_shell => 0,
make_main => 0,
verilator_flags2 => [
'--exe',
'--trace',
"$Self->{t_dir}/t_forceable_var.cpp",
"$Self->{t_dir}/t_forceable_var.vlt"
],
);
execute(
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
ok(1);
1;