forked from github/verilator
f8c0169e82
Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code.
31 lines
756 B
Perl
Executable File
31 lines
756 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_forceable_net.v");
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compile(
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make_top_shell => 0,
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make_main => 0,
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verilator_flags2 => [
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'-DCMT=1',
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'--exe',
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"$Self->{t_dir}/t_forceable_net.cpp"
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],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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