forked from github/verilator
57 lines
1.2 KiB
Systemverilog
57 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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parameter CNT = 5;
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wire [31:0] w [CNT:0];
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generate
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for (genvar g=0; g<CNT; g++)
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sub sub (.clk(clk), .i(w[g]), .z(w[g+1]));
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endgenerate
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reg [31:0] w0;
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assign w[0] = w0;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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w0 = 32'h1234;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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`define EXPECTED_SUM 32'h1239
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d sum=%x\n", $time, cyc, w[CNT]);
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`endif
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if (w[CNT] !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (input clk, input [31:0] i, output [31:0] z);
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logic [31:0] z_tmp /* verilator public */;
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always @(posedge clk)
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z_tmp <= i+1+$c("0"); // $c so doesn't optimize away
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assign z = z_tmp;
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endmodule
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