forked from github/verilator
80 lines
2.5 KiB
Systemverilog
80 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [32:0] in = crc[32:0];
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logic bank_rd_vec_m3;
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always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33];
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logic [3:0][31:0] data_i;
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wire [3:0] out;
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for (genvar i = 0; i < 4; ++i) begin
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always_ff @(posedge clk) data_i[i] <= crc[63:32];
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ecc_check_pipe u_bank_data_ecc_check(
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.clk (clk),
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.bank_rd_m3 (bank_rd_vec_m3),
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.data_i ({1'b0, data_i[i]}),
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.ecc_err_o (out[i])
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);
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end
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'b0, out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'ha2601675a6ae4972
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module ecc_check_pipe (
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input logic clk,
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input logic bank_rd_m3,
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input logic [32:0] data_i,
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output logic ecc_err_o
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);
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logic [3:0] check_group_6_0;
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logic check_group_6_0_q;
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always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7] };
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always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <=^check_group_6_0;
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assign ecc_err_o = check_group_6_0_q;
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endmodule
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