forked from github/verilator
130 lines
3.8 KiB
Systemverilog
130 lines
3.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish;
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// on success, or $stop.
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//
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// The code as shown applies a random vector to the Test
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// module, then calculates a CRC on the Test module's outputs.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here, otherwise:**
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [7:0] in = crc[7:0];
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/*AUTOWIRE*/
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wire out0;
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wire out1;
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wire out2;
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wire out3;
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wire out4;
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wire out5;
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wire out6;
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wire out7;
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/*SelFlop AUTO_TEMPLATE(.n(@),
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.out(out@)); */
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SelFlop selflop0(/*AUTOINST*/
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// Outputs
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.out (out0), // Templated
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// Inputs
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.clk (clk),
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.in (in[7:0]),
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.n (0)); // Templated
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SelFlop selflop1(/*AUTOINST*/
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// Outputs
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.out (out1), // Templated
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// Inputs
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.clk (clk),
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.in (in[7:0]),
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.n (1)); // Templated
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SelFlop selflop2(/*AUTOINST*/
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// Outputs
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.out (out2), // Templated
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// Inputs
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.clk (clk),
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.in (in[7:0]),
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.n (2)); // Templated
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SelFlop selflop3(/*AUTOINST*/
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// Outputs
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.out (out3), // Templated
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// Inputs
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.clk (clk),
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.in (in[7:0]),
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.n (3)); // Templated
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// Aggregate outputs into a single result vector
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wire outo = out0|out1|out2|out3;
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wire outa = out0&out1&out2&out3;
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wire outx = out0^out1^out2^out3;
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wire [63:0] result = {61'h0, outo, outa, outx};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h118c5809c7856d78
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module SelFlop(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in, n
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);
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input clk;
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input [7:0] in;
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input [2:0] n;
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output reg out;
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// verilator no_inline_module
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always @(posedge clk) begin
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out <= in[n];
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end
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endmodule
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