forked from github/verilator
39 lines
951 B
Systemverilog
39 lines
951 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Cls;
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int imembera;
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int imemberb;
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endclass : Cls
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module t (/*AUTOARG*/);
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typedef Cls Cls2;
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initial begin
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Cls c;
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Cls2 c2;
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if (c != null) $stop;
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if (c) $stop;
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if (c2) $stop;
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$display("Display: null = \"%p\"", c); // null
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c = new;
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c2 = new;
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if (c == null) $stop;
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if (!c) $stop;
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if (!c2) $stop;
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$display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0}
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c.imembera = 10;
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c.imemberb = 20;
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$display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20}
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if (c.imembera != 10) $stop;
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if (c.imemberb != 20) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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