forked from github/verilator
Fix typedef'ed class conversion to boolean (#3616).
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@ -13,7 +13,8 @@ Verilator 4.227 devel
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**Minor:**
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Fix crash in gate optimization of circular logic (#3543). [Bill Flynn]
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* Fix crash in gate optimization of circular logic (#3543). [Bill Flynn]
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* Fix typedef'ed class conversion to boolean (#3616). [Aleksander Kiryk]
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Verilator 4.226 2022-08-31
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@ -5808,7 +5808,8 @@ private:
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"Node has no type"); // Perhaps forgot to do a prelim visit on it?
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//
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// For DOUBLE under a logical op, add implied test against zero, never a warning
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if (underp && underp->isDouble()) {
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AstNodeDType* const underVDTypep = underp ? underp->dtypep()->skipRefp() : nullptr;
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if (underp && underVDTypep->isDouble()) {
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UINFO(6, " spliceCvtCmpD0: " << underp << endl);
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VNRelinker linker;
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underp->unlinkFrBack(&linker);
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@ -5816,13 +5817,12 @@ private:
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= new AstNeqD(nodep->fileline(), underp,
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new AstConst(nodep->fileline(), AstConst::RealDouble(), 0.0));
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linker.relink(newp);
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} else if (VN_IS(underp->dtypep(), ClassRefDType)
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|| (VN_IS(underp->dtypep(), BasicDType)
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&& VN_AS(underp->dtypep(), BasicDType)->keyword()
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== VBasicDTypeKwd::CHANDLE)) {
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} else if (VN_IS(underVDTypep, ClassRefDType)
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|| (VN_IS(underVDTypep, BasicDType)
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&& VN_AS(underVDTypep, BasicDType)->keyword() == VBasicDTypeKwd::CHANDLE)) {
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// Allow warning-free "if (handle)"
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VL_DO_DANGLING(fixWidthReduce(underp), underp); // Changed
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} else if (!underp->dtypep()->basicp()) {
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} else if (!underVDTypep->basicp()) {
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nodep->v3error("Logical operator " << nodep->prettyTypeName()
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<< " expects a non-complex data type on the "
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<< side << ".");
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@ -12,14 +12,20 @@ class Cls;
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endclass : Cls
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module t (/*AUTOARG*/);
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typedef Cls Cls2;
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initial begin
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Cls c;
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Cls2 c2;
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if (c != null) $stop;
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if (c) $stop;
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if (c2) $stop;
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$display("Display: null = \"%p\"", c); // null
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c = new;
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c2 = new;
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if (c == null) $stop;
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if (!c) $stop;
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if (!c2) $stop;
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$display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0}
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c.imembera = 10;
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c.imemberb = 20;
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