forked from github/verilator
58 lines
939 B
Systemverilog
58 lines
939 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Peter Monsson.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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Test test (/*AUTOINST*/
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// Inputs
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.clk (clk));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test
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(
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input clk
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);
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`ifdef FAIL_ASSERT_1
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assert property (
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@(posedge clk)
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1 |-> 0
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) else $display("[%0t] wrong implication", $time);
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`endif
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assert property (
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@(posedge clk)
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1 |-> 1
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);
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assert property (
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@(posedge clk)
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0 |-> 0
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);
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assert property (
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@(posedge clk)
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0 |-> 1
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);
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endmodule
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