forked from github/verilator
Support implication operator "|->" in assertions, #2069.
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
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@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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*** Support bounded queues.
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*** Support implication operator "|->" in assertions, #2069. [Peter Monsson]
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*** Support string compare, ato*, etc methods, #1606. [Yutetsu TAKATSUKASA]
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**** Support immediate cover statements.
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@ -4254,13 +4254,21 @@ elseStmtBlock<nodep>: // Part of concurrent_assertion_statement
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property_spec<nodep>: // IEEE: property_spec
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//UNSUP: This rule has been super-specialized to what is supported now
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'@' '(' senitemEdge ')' yDISABLE yIFF '(' expr ')' expr
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'@' '(' senitemEdge ')' yDISABLE yIFF '(' expr ')' property_expr
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{ $$ = new AstPropClocked($1, $3, $8, $10); }
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| '@' '(' senitemEdge ')' expr { $$ = new AstPropClocked($1, $3, NULL, $5); }
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| yDISABLE yIFF '(' expr ')' expr { $$ = new AstPropClocked($4->fileline(), NULL, $4, $6); }
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| expr { $$ = new AstPropClocked($1->fileline(), NULL, NULL, $1); }
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| '@' '(' senitemEdge ')' property_expr { $$ = new AstPropClocked($1, $3, NULL, $5); }
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| yDISABLE yIFF '(' expr ')' property_expr { $$ = new AstPropClocked($4->fileline(), NULL, $4, $6); }
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| property_expr { $$ = new AstPropClocked($1->fileline(), NULL, NULL, $1); }
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;
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property_expr<nodep>: // IEEE: property_expr
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//UNSUP: This rule has been super-specialized to what is supported now
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expr yP_ORMINUSGT property_expr { $$ = new AstLogOr($2,new AstLogNot($2,$1),$3); }
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//UNSUP expr yP_OREQGT property_expr { $$ = new AstLogOr($2,new AstLogNot($2,new AstPast($2,$1, NULL)),$3); } // This handles disable iff in the past time step incorrectly
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| expr { $$ = $1; }
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;
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//************************************************
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// Let
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21
test_regress/t/t_assert_implication.pl
Executable file
21
test_regress/t/t_assert_implication.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ['--assert --cc'],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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57
test_regress/t/t_assert_implication.v
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57
test_regress/t/t_assert_implication.v
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@ -0,0 +1,57 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Peter Monsson.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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Test test (/*AUTOINST*/
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// Inputs
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.clk (clk));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test
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(
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input clk
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);
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`ifdef FAIL_ASSERT_1
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assert property (
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@(posedge clk)
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1 |-> 0
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) else $display("[%0t] wrong implication", $time);
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`endif
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assert property (
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@(posedge clk)
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1 |-> 1
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);
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assert property (
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@(posedge clk)
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0 |-> 0
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);
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assert property (
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@(posedge clk)
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0 |-> 1
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);
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endmodule
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26
test_regress/t/t_assert_implication_bad.pl
Executable file
26
test_regress/t/t_assert_implication_bad.pl
Executable file
@ -0,0 +1,26 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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top_filename("t/t_assert_implication.v");
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compile(
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v_flags2 => ['+define+FAIL_ASSERT_1'],
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verilator_flags2 => ['--assert --cc'],
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);
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execute(
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);
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# We expect to get a message when this assert fires:
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file_grep($Self->{run_log_filename}, qr/wrong implication/);
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ok(1);
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1;
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