forked from github/verilator
240 lines
8.3 KiB
Systemverilog
240 lines
8.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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ign, ign2, ign3, ign4, ign4s,
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// Inputs
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clk
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);
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input clk;
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output [31:0] ign;
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output [3:0] ign2;
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output [11:0] ign3;
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parameter [95:0] P6 = 6;
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localparam P64 = (1 << P6);
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// verilator lint_off WIDTH
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localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
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localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
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// verilator lint_on WIDTH
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reg [31:0] iright;
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reg signed [31:0] irights;
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reg [31:0] ileft;
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reg [P64-1:0] qright;
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reg signed [P64-1:0] qrights;
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reg [P64-1:0] qleft;
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reg [95:0] wright;
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reg signed [95:0] wrights;
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reg [95:0] wleft;
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reg [31:0] q_iright;
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reg signed [31:0] q_irights;
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reg [31:0] q_ileft;
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reg [P64-1:0] q_qright;
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reg signed [P64-1:0] q_qrights;
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reg [P64-1:0] q_qleft;
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reg [95:0] q_wright;
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reg signed [95:0] q_wrights;
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reg [95:0] q_wleft;
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reg [31:0] w_iright;
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reg signed [31:0] w_irights;
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reg [31:0] w_ileft;
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reg [P64-1:0] w_qright;
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reg signed [P64-1:0] w_qrights;
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reg [P64-1:0] w_qleft;
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reg [95:0] w_wright;
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reg signed [95:0] w_wrights;
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reg [95:0] w_wleft;
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reg [31:0] iamt;
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reg [63:0] qamt;
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reg [95:0] wamt;
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assign ign = {31'h0, clk} >>> 4'bx; // bug760
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assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174
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assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}},
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iamt[1:0] >> {11{iamt[5:2]}},
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$signed(iamt[1:0]) >>> {22{iamt[5:2]}},
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$signed(iamt[1:0]) >>> {11{iamt[5:2]}},
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iamt[1:0] << {22{iamt[5:2]}},
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iamt[1:0] << {11{iamt[5:2]}}};
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wire [95:0] wamtt = {iamt,iamt,iamt};
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output wire [95:0] ign4;
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assign ign4 = wamtt >> {11{iamt[5:2]}};
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output wire signed [95:0] ign4s;
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assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}};
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always @* begin
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iright = 32'h819b018a >> iamt;
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irights = 32'sh819b018a >>> signed'(iamt);
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ileft = 32'h819b018a << iamt;
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qright = 64'hf784bf8f_12734089 >> iamt;
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qrights = 64'shf784bf8f_12734089 >>> signed'(iamt);
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qleft = 64'hf784bf8f_12734089 << iamt;
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wright = 96'hf784bf8f_12734089_190abe48 >> iamt;
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wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt);
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wleft = 96'hf784bf8f_12734089_190abe48 << iamt;
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q_iright = 32'h819b018a >> qamt;
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q_irights = 32'sh819b018a >>> signed'(qamt);
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q_ileft = 32'h819b018a << qamt;
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q_qright = 64'hf784bf8f_12734089 >> qamt;
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q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt);
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q_qleft = 64'hf784bf8f_12734089 << qamt;
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q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt;
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q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt);
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q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt;
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w_iright = 32'h819b018a >> wamt;
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w_irights = 32'sh819b018a >>> signed'(wamt);
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w_ileft = 32'h819b018a << wamt;
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w_qright = 64'hf784bf8f_12734089 >> wamt;
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w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt);
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w_qleft = 64'hf784bf8f_12734089 << wamt;
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w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt;
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w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt);
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w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt;
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end
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright);
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`endif
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if (cyc==1) begin
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iamt <= 0;
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qamt <= 0;
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wamt <= 0;
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if (P64 != 64) $stop;
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if (5'b10110>>2 != 5'b00101) $stop;
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if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
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if (5'b10110<<2 != 5'b11000) $stop;
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if (5'b10110<<<2 != 5'b11000) $stop;
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if (5'sb10110>>2 != 5'sb00101) $stop;
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if (5'sb10110>>>2 != 5'sb11101) $stop;
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if (5'sb10110<<2 != 5'sb11000) $stop;
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if (5'sb10110<<<2 != 5'sb11000) $stop;
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// Allow >64 bit shifts if the shift amount is a constant
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if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
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end
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if (cyc==2) begin
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iamt <= 28;
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qamt <= 28;
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wamt <= 28;
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if (ileft != 32'h819b018a) $stop;
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if (iright != 32'h819b018a) $stop;
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if (irights != 32'h819b018a) $stop;
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if (qleft != 64'hf784bf8f_12734089) $stop;
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if (qright != 64'hf784bf8f_12734089) $stop;
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if (qrights != 64'hf784bf8f_12734089) $stop;
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if (wleft != 96'hf784bf8f12734089190abe48) $stop;
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if (wright != 96'hf784bf8f12734089190abe48) $stop;
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if (wrights != 96'hf784bf8f12734089190abe48) $stop;
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end
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if (cyc==3) begin
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iamt <= 31;
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qamt <= 31;
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wamt <= 31;
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if (ileft != 32'ha0000000) $stop;
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if (iright != 32'h8) $stop;
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if (irights != 32'hfffffff8) $stop;
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if (qleft != 64'hf127340890000000) $stop;
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if (qright != 64'h0000000f784bf8f1) $stop;
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if (qrights != 64'hffffffff784bf8f1) $stop;
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if (wleft != 96'hf12734089190abe480000000) $stop;
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if (wright != 96'h0000000f784bf8f127340891) $stop;
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if (wrights != 96'hffffffff784bf8f127340891) $stop;
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end
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if (cyc==4) begin
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iamt <= 32;
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qamt <= 32;
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wamt <= 32;
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if (ileft != 32'h0) $stop;
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if (iright != 32'h1) $stop;
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if (qleft != 64'h8939a04480000000) $stop;
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if (qright != 64'h00000001ef097f1e) $stop;
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end
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if (cyc==5) begin
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iamt <= 33;
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qamt <= 33;
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wamt <= 33;
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if (ileft != 32'h0) $stop;
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if (iright != 32'h0) $stop;
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if (qleft != 64'h1273408900000000) $stop;
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if (qright != 64'h00000000f784bf8f) $stop;
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end
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if (cyc==6) begin
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iamt <= 64;
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qamt <= 64;
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wamt <= 64;
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if (ileft != 32'h0) $stop;
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if (iright != 32'h0) $stop;
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if (qleft != 64'h24e6811200000000) $stop;
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if (qright != 64'h000000007bc25fc7) $stop;
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end
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if (cyc==7) begin
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iamt <= 128;
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qamt <= 128;
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wamt <= 128;
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if (ileft != 32'h0) $stop;
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if (iright != 32'h0) $stop;
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if (qleft != 64'h0) $stop;
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if (qright != 64'h0) $stop;
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end
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if (cyc==8) begin
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iamt <= 100;
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qamt <= {32'h10, 32'h0};
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wamt <= {32'h10, 64'h0};
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if (ileft != '0) $stop;
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if (iright != '0) $stop;
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if (irights != '1) $stop;
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if (qleft != '0) $stop;
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if (qright != '0) $stop;
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if (qrights != '1) $stop;
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if (wleft != '0) $stop;
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if (wright != '0) $stop;
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if (wrights != '1) $stop;
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end
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if (cyc==19) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// General rule to test all q's
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if (cyc != 0) begin
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if (ileft != q_ileft) $stop;
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if (iright != q_iright) $stop;
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if (irights != q_irights) $stop;
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if (qleft != q_qleft) $stop;
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if (qright != q_qright) $stop;
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if (qrights != q_qrights) $stop;
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if (wleft != q_wleft) $stop;
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if (wright != q_wright) $stop;
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if (wrights != q_wrights) $stop;
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if (ileft != w_ileft) $stop;
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if (iright != w_iright) $stop;
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if (irights != w_irights) $stop;
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if (qleft != w_qleft) $stop;
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if (qright != w_qright) $stop;
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if (qrights != w_qrights) $stop;
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if (wleft != w_wleft) $stop;
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if (wright != w_wright) $stop;
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if (wrights != w_wrights) $stop;
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end
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end
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end
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endmodule
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