forked from github/verilator
101 lines
2.6 KiB
Systemverilog
101 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg [127:0] in;
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check #(48) check48 (.*);
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check #(31) check31 (.*);
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check #(32) check32 (.*);
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check #(63) check63 (.*);
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check #(64) check64 (.*);
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check #(96) check96 (.*);
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check #(128) check128 (.*);
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always_comb begin
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if (crc[2:0] == 0) in = '0;
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else if (crc[2:0] == 1) in = ~'0;
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else if (crc[2:0] == 2) in = 128'b1;
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else if (crc[2:0] == 3) in = ~ 128'b1;
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else begin
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in = {crc, crc};
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if (crc[3]) in[31:0] = '0;
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if (crc[4]) in[63:32] = '0;
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if (crc[5]) in[95:64] = '0;
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if (crc[6]) in[127:96] = '0;
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if (crc[7]) in[31:0] = ~'0;
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if (crc[8]) in[63:32] = ~'0;
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if (crc[9]) in[95:64] = ~'0;
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if (crc[10]) in[127:96] = ~'0;
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end
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d in=%x\n", $time, cyc, in);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc == 99) begin
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`checkr(check48.sum, 14574057015683440.000000);
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`checkr(check31.sum, 114141374814.000000);
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`checkr(check32.sum, 236547942750.000000);
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`checkr(check63.sum, 513694866079917670400.000000);
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`checkr(check64.sum, 1002533584033221181440.000000);
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`checkr(check96.sum, 4377373669974269260279175970816.000000);
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`checkr(check128.sum, 18358899571808044815012294240949812330496.000000);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module check(/*AUTOARG*/
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// Inputs
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in, clk, cyc
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);
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parameter WIDTH = 128;
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input [127:0] in;
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wire [WIDTH-1:0] ci = in[WIDTH-1:0];
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wire signed [WIDTH-1:0] cis = in[WIDTH-1:0];
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real r;
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real rs;
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always_comb r = ci;
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always_comb rs = cis;
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input clk;
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input integer cyc;
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real sum;
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always_ff @ (negedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum);
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`endif
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if (cyc < 10) sum <= 0;
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else sum <= sum + r + rs;
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end
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endmodule
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