Geza Lore 599d23697d IEEE compliant scheduler (#3384) ... This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278		2022-05-15 16:03:32 +01:00
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t	IEEE compliant scheduler (#3384)	2022-05-15 16:03:32 +01:00
.gdbinit
.gitignore
CMakeLists.txt	Copyright year update.	2022-01-01 08:26:40 -05:00
driver.pl	Deprecate 'vluint64_t' and similar types (#3255).	2022-03-27 15:27:40 -04:00
input.vc
input.xsim.vc
Makefile	Copyright year update.	2022-01-01 08:26:40 -05:00
Makefile_obj	Implement 'forceable' attribute	2022-01-16 15:31:37 +00:00