forked from github/verilator
54 lines
811 B
Verilog
54 lines
811 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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q,
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// Inputs
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clk, d
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);
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input clk;
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input [3:0] d;
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output wire [3:0] q;
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logic [3:0] between;
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mod1 cell1 (.q(between),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.d (d[3:0]));
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mod2 cell2 (.d(between),
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/*AUTOINST*/
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// Outputs
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.q (q[3:0]),
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// Inputs
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.clk (clk));
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endmodule
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module mod1
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(
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input clk,
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input [3:0] d,
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output logic [3:0] q
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);
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always @(posedge clk)
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q <= d;
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endmodule
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module mod2
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(
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input clk,
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input [3:0] d,
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output wire [3:0] q
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);
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assign q = d;
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endmodule
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