forked from github/verilator
17 lines
329 B
Verilog
17 lines
329 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t;
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subok subok (.a(1'b1), .b(1'b0));
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sub sub (.a(1'b1), .b(1'b0));
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endmodule
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module subok (input a,b);
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endmodule
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module sub (a);
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input a, b;
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endmodule
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