forked from github/verilator
31 lines
984 B
Perl
Executable File
31 lines
984 B
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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# Access is so we can dump waves
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v_flags2 => [$Self->{v3}?'-trace':' +access+rwc'],
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);
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execute (
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check_finished=>1,
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);
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if ($Self->{vlt}) {
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file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
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my $sig = quotemeta("bra[ket]slash/dash-colon:9");
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file_grep ("$Self->{obj_dir}/simx.vcd", qr/ $sig/);
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file_grep ("$Self->{obj_dir}/simx.vcd", qr/ other\.cyc /);
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file_grep ("$Self->{obj_dir}/simx.vcd", qr/ module mod\.with_dot /);
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vcd_identical ("$Self->{obj_dir}/simx.vcd",
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"t/$Self->{name}.out");
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}
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ok(1);
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1;
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