forked from github/verilator
de1bb5aeb6
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
164 lines
2.1 KiB
Plaintext
164 lines
2.1 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Tue Jul 24 18:44:43 2012
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 * 9num $end
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$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end
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$var wire 1 ' clk $end
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$var wire 1 ) double__underscore $end
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$var wire 1 ( escaped_normal $end
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$scope module v $end
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$var wire 1 * 9num $end
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$var wire 32 & a0.cyc [31:0] $end
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$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end
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$var wire 1 $ check:alias $end
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$var wire 1 % check;alias $end
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$var wire 1 $ check_alias $end
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$var wire 1 ' clk $end
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$var wire 32 # cyc [31:0] $end
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$var wire 1 ) double__underscore $end
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$var wire 1 ( escaped_normal $end
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$var wire 32 & other.cyc [31:0] $end
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$var wire 1 $ wire $end
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$scope module a0 $end
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$var wire 32 # cyc [31:0] $end
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$upscope $end
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$scope module mod.with_dot $end
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$var wire 32 # cyc [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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1$
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b00000000000000000000000000000001 #
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