forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
26 lines
435 B
Verilog
26 lines
435 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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// Check that the lint_on is obeyed.
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// verilator lint_off VARHIDDEN
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// verilator lint_on VARHIDDEN
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integer top;
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task x;
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output top;
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begin end
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endtask
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initial begin
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begin: lower
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integer top;
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end
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end
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endmodule
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