forked from github/verilator
48 lines
758 B
Verilog
48 lines
758 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg a;
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wire o;
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udp (o, a);
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integer cyc; initial cyc=0;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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a <= cyc[0];
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if (cyc==0) begin
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end
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else if (cyc<90) begin
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if (a != !cyc[0]) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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primitive udp(o,a);
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output o;
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input a;
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`ifdef verilator
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wire o = ~a;
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`else
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table
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//o a
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0 : 1;
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1 : 0;
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endtable
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`endif
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endprimitive
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