forked from github/verilator
148 lines
3.7 KiB
Verilog
148 lines
3.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] out; // From test of Test.v
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// End of automatics
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// Async clears must not race with clocks if we want repeatable results
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reg set_l = in[20];
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reg clr_l = in[21];
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always @ (negedge clk) begin
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set_l <= in[20];
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clr_l <= in[21];
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end
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//====== Mux
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wire [1:0] qm;
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// delay z a b sel
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udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]);
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udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]);
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`define verilatorxx
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`ifdef verilatorxx
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reg [1:0] ql;
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reg [1:0] qd;
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// No sequential tables, yet
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// always @* begin
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// if (!clk) ql = in[13:12];
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// end
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always @(posedge clk or negedge set_l or negedge clr_l) begin
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if (!set_l) qd <= ~2'b0;
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else if (!clr_l) qd <= 2'b0;
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else qd <= in[17:16];
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end
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`else
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//====== Latch
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// wire [1:0] ql;
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// // q clk d
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// udp_latch l0 (ql[0], !in[8], in[12]);
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// udp_latch l1 (ql[1], !in[8], in[13]);
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//====== DFF
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wire [1:0] qd;
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//always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]);
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// q clk d set_l clr_l
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udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l);
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udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l);
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`endif
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// Aggregate outputs into a single result vector
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wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm};
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// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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// Note not all simulators agree about the latch result. Maybe have a race?
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`define EXPECTED_SUM 64'hb73acf228acaeaa3
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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primitive udp_mux2 (z, a, b, sel);
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output z;
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input a, b, sel;
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table
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//a b s o
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? 1 1 : 1 ;
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? 0 1 : 0 ;
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1 ? 0 : 1 ;
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0 ? 0 : 0 ;
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1 1 x : 1 ;
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0 0 x : 0 ;
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endtable
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endprimitive
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primitive udp_latch (q, clk, d);
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output q; reg q;
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input clk, d;
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table
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//clk d q q'
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0 1 : ? : 1;
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0 0 : ? : 0;
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1 ? : ? : -;
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endtable
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endprimitive
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primitive udp_dff (q, clk, d, set_l, clr_l);
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output q;
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input clk, d, set_l, clr_l;
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reg q;
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table
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//ck d s c : q : q'
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r 0 1 ? : ? : 0 ;
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r 1 ? 1 : ? : 1 ;
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* 1 ? 1 : 1 : 1 ;
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* 0 1 ? : 0 : 0 ;
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f ? ? ? : ? : - ;
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b * ? ? : ? : - ;
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? ? 0 ? : ? : 1 ;
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b ? * 1 : 1 : 1 ;
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x 1 * 1 : 1 : 1 ;
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? ? 1 0 : ? : 0 ;
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b ? 1 * : 0 : 0 ;
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x 0 1 * : 0 : 0 ;
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endtable
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endprimitive
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