forked from github/verilator
27 lines
565 B
Verilog
27 lines
565 B
Verilog
// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Lane Brooks
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module top (input A, input OE, output X, output Y, output Z);
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pullup p1(Z);
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assign Z = OE ? A : 1'bz;
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pulldown p2(Y);
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assign Y = OE ? A : 1'bz;
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pass pass(.A(A), .OE(OE), .X(X));
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pullup_module p(X);
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endmodule
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module pass (input A, input OE, inout X);
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io io(.A(A), .OE(OE), .X(X));
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endmodule
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module io (input A, input OE, inout X);
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assign X = (OE) ? A : 1'bz;
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endmodule
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module pullup_module (output X);
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pullup p1(X);
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endmodule
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