forked from github/verilator
13 lines
202 B
Verilog
13 lines
202 B
Verilog
// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Lane Brooks.
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module t (clk);
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input clk;
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wire A;
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pullup p1(A);
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pulldown p2(A);
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endmodule
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