forked from github/verilator
76 lines
1.3 KiB
Verilog
76 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (
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input wire CLK,
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output reg RESET
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);
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neg neg (.clk(CLK));
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little little (.clk(CLK));
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glbl glbl ();
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// A vector
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logic [2:1] vec [4:3];
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integer val = 0;
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always @ (posedge CLK) begin
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if (RESET) val <= 0;
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else val <= val + 1;
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vec[3] <= val[1:0];
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vec[4] <= val[3:2];
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end
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initial RESET = 1'b1;
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always @ (posedge CLK)
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RESET <= glbl.GSR;
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endmodule
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module glbl();
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`ifdef PUB_FUNC
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wire GSR;
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task setGSR;
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/* verilator public */
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input value;
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GSR = value;
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endtask
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`else
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wire GSR /*verilator public*/;
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`endif
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endmodule
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module neg (
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input clk
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);
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reg [0:-7] i8; initial i8 = '0;
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reg [-1:-48] i48; initial i48 = '0;
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reg [63:-64] i128; initial i128 = '0;
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always @ (posedge clk) begin
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i8 <= ~i8;
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i48 <= ~i48;
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i128 <= ~i128;
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end
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endmodule
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module little (
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input clk
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);
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// verilator lint_off LITENDIAN
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reg [0:7] i8; initial i8 = '0;
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reg [1:49] i48; initial i48 = '0;
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reg [63:190] i128; initial i128 = '0;
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// verilator lint_on LITENDIAN
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always @ (posedge clk) begin
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i8 <= ~i8;
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i48 <= ~i48;
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i128 <= ~i128;
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end
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endmodule
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