forked from github/verilator
491 lines
5.0 KiB
Plaintext
491 lines
5.0 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Sat Feb 23 20:39:34 2013
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 $ clk $end
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$scope module v $end
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$var wire 1 $ clk $end
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$var wire 32 # cyc [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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