forked from github/verilator
f19ba9d54d
Tracing negative indexes requires latest Verilog-Perl and SystemPerl. (Merged from negative_lsb branch.)
70 lines
1.9 KiB
Verilog
70 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [15:-16] sel2 = crc[31:0];
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wire [80:-10] sel3 = {crc[26:0],crc};
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wire [3:0] out21 = sel2[-3 : -6];
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wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
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wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
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wire [3:0] out31 = sel3[-3 : -6];
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wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
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wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
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// Aggregate outputs into a single result vector
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wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
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reg [15:-16] sel1;
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initial begin
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// Path clearing
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sel1 = 32'h12345678;
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if (sel1 != 32'h12345678) $stop;
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if (sel1[-13 : -16] != 4'h8) $stop;
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if (sel1[3:0] != 4'h4) $stop;
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if (sel1[4 +: 4] != 4'h3) $stop;
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if (sel1[11 -: 4] != 4'h2) $stop;
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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`define EXPECTED_SUM 64'hba7fe1e7ac128362
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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