forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg toggle;
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integer cyc; initial cyc=1;
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wire [7:0] cyc_copy = cyc[7:0];
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// psl cover {cyc==3 || cyc==4} @ (posedge clk);
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// psl assert {cyc<100} @ (posedge clk) report "AssertionFalse1";
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`ifdef FAILING_ASSERTIONS
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// psl assert {toggle} @ (posedge clk) report "AssertionShouldFail";
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`endif
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// psl default clock = negedge clk;
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//FIX // psl assert always {cyc<99};
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// psl cover {cyc==9} report "DefaultClock,expect=1";
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// psl assert {(cyc==5)->toggle};
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// psl cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
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`ifdef NOT_SUP
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// psl assert {toggle<->cyc[0]};
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// psl cover {toggle<->cyc[0]} report "CycsLogIff,expect=10";
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`endif
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// Test {{..}} == Sequence of sequence...
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// psl assert {{true}};
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always @ (negedge clk) begin
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//if (!(cyc==5) || toggle) $write("%d: %s\n", cyc, "ToggleLogIf,expect=1");
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//if (toggle&&cyc[0] || ~toggle&&~cyc[0]) $write("%d: %s\n", cyc, "CycsLogIff,expect=10");
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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toggle <= !cyc[0];
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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