forked from github/verilator
21 lines
321 B
Verilog
21 lines
321 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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`define CHECK text \
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multiline
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Hello in t_preproc_psl.v
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`ifdef NEVER
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not
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`else
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yes
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`endif
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Multi `CHECK line
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// Did we end up right?
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Line: `__LINE__
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