forked from github/verilator
13 lines
278 B
Verilog
13 lines
278 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t (/*AUTOARG*/);
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sub sub ();
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endmodule
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module sub #(parameter WIDTH=X, parameter X=WIDTH)
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();
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endmodule
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