forked from github/verilator
36 lines
621 B
Verilog
36 lines
621 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett
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// see bug 591
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package pkg2;
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parameter PARAM2 = 16;
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endpackage // pkg2
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package pkg1;
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import pkg2::*;
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`ifdef T_PACKAGE_EXPORT
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export pkg2::*; // Not supported on all simulators
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`endif
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parameter PARAM1 = 8;
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endpackage // pkg1
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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import pkg1::*;
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reg [PARAM1:0] bus1;
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reg [PARAM2:0] bus2;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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