forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
18 lines
264 B
Verilog
18 lines
264 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module a();
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endmodule
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module test();
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a a();
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endmodule
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module a();
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endmodule
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module b();
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endmodule
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