forked from github/verilator
16 lines
409 B
Verilog
16 lines
409 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t ();
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// This isn't a width violation, as +/- 1'b1 is a common idiom
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// that's fairly harmless
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wire [4:0] five = 5'd5;
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wire [4:0] suma = five + 1'b1;
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wire [4:0] sumb = 1'b1 + five;
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wire [4:0] sumc = five - 1'b1;
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endmodule
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