forked from github/verilator
35 lines
573 B
Verilog
35 lines
573 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t
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(
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input wire reset_l,
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input wire clk
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);
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sub sub_I
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(
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.clk(clk),
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.reset_l(reset_l),
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.cpu_if_timeout(1'b0)
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);
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endmodule
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module sub
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(
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input wire clk, reset_l,
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output reg cpu_if_timeout
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);
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always @(posedge clk) begin
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if (!reset_l) begin
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cpu_if_timeout <= 1'b0;
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end
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else begin
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cpu_if_timeout <= 1'b0;
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end
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end
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endmodule
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