forked from github/verilator
20 lines
471 B
Verilog
20 lines
471 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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// Check that we report warnings only once on parameterized modules
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// Also check that we don't suppress warnings on the same line
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module t ();
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sub #(.A(1)) sub1();
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sub #(.A(2)) sub2();
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sub #(.A(3)) sub3();
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endmodule
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module sub;
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parameter A = 0;
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reg [A:0] unus1; reg [A:0] unus2;
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endmodule
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