forked from github/verilator
24 lines
429 B
Verilog
24 lines
429 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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//bug485, but see t_gen_forif.v for an OK example.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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always_comb begin
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integer i;
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for(i=0; i<10; i++ ) begin: COMB
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end
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for(i=0; i<9; i++ ) begin: COMB
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end
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end
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endmodule
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