forked from github/verilator
48 lines
840 B
Verilog
48 lines
840 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer i;
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reg sync_blk;
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reg sync_blk2;
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reg sync_nblk;
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reg sync2_ok;
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reg sync3_ok;
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reg combo_blk;
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reg combo_nblk;
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always @(posedge clk) begin
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sync_blk = 1'b1;
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sync_blk2 = 1'b1; // Only warn once per block
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sync_nblk <= 1'b1;
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end
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always @* begin
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combo_blk = 1'b1;
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combo_nblk <= 1'b1;
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end
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always @(posedge clk) begin
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for (int i=0; i<20; i++) begin
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sync2_ok <= 1'b1;
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end
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end
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always @(posedge clk) begin
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sync3_ok <= f(sync3_ok);
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end
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function f (input v);
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f = ~v;
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endfunction
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endmodule
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