forked from github/verilator
29 lines
622 B
Verilog
29 lines
622 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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interface pads_if();
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modport mp_dig(
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import fIn,
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import fOut );
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integer exists[8];
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function automatic integer fIn (integer i);
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fIn = exists[i];
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endfunction
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task automatic fOut (integer i);
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exists[i] = 33;
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endtask
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endinterface
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module t();
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pads_if padsif();
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initial begin
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padsif.fOut(3);
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if (padsif.fIn(3) != 33) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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