forked from github/verilator
132 lines
3.1 KiB
Verilog
132 lines
3.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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interface counter_if;
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logic [3:0] value;
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logic reset;
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modport counter_mp (input reset, output value);
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modport core_mp (output reset, input value);
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endinterface
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// Check can have inst module before top module
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module counter_ansi
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(
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input clkm,
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counter_if c_data,
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input logic [3:0] i_value
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);
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always @ (posedge clkm) begin
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c_data.value <= c_data.reset ? i_value : c_data.value + 1;
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end
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endmodule : counter_ansi
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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counter_if c1_data();
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counter_if c2_data();
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counter_if c3_data();
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counter_if c4_data();
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counter_ansi c1 (.clkm(clk),
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.c_data(c1_data.counter_mp),
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.i_value(4'h1));
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`ifdef VERILATOR counter_ansi `else counter_nansi `endif
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/**/ c2 (.clkm(clk),
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.c_data(c2_data.counter_mp),
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.i_value(4'h2));
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counter_ansi_m c3 (.clkm(clk),
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.c_data(c3_data),
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.i_value(4'h3));
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`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif
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/**/ c4 (.clkm(clk),
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.c_data(c4_data),
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.i_value(4'h4));
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initial begin
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c1_data.value = 4'h4;
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c2_data.value = 4'h5;
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c3_data.value = 4'h6;
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c4_data.value = 4'h7;
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end
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc<2) begin
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c1_data.reset <= 1;
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c2_data.reset <= 1;
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c3_data.reset <= 1;
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c4_data.reset <= 1;
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end
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if (cyc==2) begin
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c1_data.reset <= 0;
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c2_data.reset <= 0;
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c3_data.reset <= 0;
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c4_data.reset <= 0;
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end
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if (cyc==20) begin
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$write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc,
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c1_data.value, c1_data.reset,
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c2_data.value, c2_data.reset,
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c3_data.value, c3_data.reset,
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c4_data.value, c4_data.reset);
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if (c1_data.value != 2) $stop;
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if (c2_data.value != 3) $stop;
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if (c3_data.value != 4) $stop;
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if (c4_data.value != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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`ifndef VERILATOR
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// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
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module counter_nansi
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(clkm, c_data, i_value);
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input clkm;
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counter_if c_data;
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input logic [3:0] i_value;
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always @ (posedge clkm) begin
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c_data.value <= c_data.reset ? i_value : c_data.value + 1;
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end
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endmodule : counter_nansi
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`endif
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module counter_ansi_m
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(
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input clkm,
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counter_if.counter_mp c_data,
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input logic [3:0] i_value
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);
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always @ (posedge clkm) begin
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c_data.value <= c_data.reset ? i_value : c_data.value + 1;
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end
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endmodule : counter_ansi_m
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`ifndef VERILATOR
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// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
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module counter_nansi_m
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(clkm, c_data, i_value);
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input clkm;
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counter_if.counter_mp c_data;
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input logic [3:0] i_value;
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always @ (posedge clkm) begin
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c_data.value <= c_data.reset ? i_value : c_data.value + 1;
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end
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endmodule : counter_nansi_m
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`endif
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