forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
55 lines
1.3 KiB
Verilog
55 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003-2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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// verilator lint_on GENCLK
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reg [31:0] long;
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reg [63:0] quad;
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wire [31:0] longout;
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wire [63:0] quadout;
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wire [7:0] narrow = long[7:0];
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sub sub (/*AUTOINST*/
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// Outputs
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.longout (longout[31:0]),
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.quadout (quadout[63:0]),
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// Inputs
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.narrow (narrow[7:0]),
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.quad (quad[63:0]));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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long <= 32'h12345678;
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quad <= 64'h12345678_abcdef12;
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end
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if (cyc==2) begin
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if (longout !== 32'h79) $stop;
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if (quadout !== 64'h12345678_abcdef13) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
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// verilator public_module
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`ifdef verilator
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wire [31:0] longout = $c32("(",narrow,"+1)");
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wire [63:0] quadout = $c64("(",quad,"+1)");
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`else
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wire [31:0] longout = narrow + 8'd1;
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wire [63:0] quadout = quad + 64'd1;
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`endif
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endmodule
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